forked from OSchip/llvm-project
Fix for PR32740 - Invalid floating type, unreachable between r300969 and r301029
The bug was introduced by r301018 "[InstCombine] fadd double (sitofp x), y check that the promotion is valid". The patch didn't expect that fadd can be on vectors not necessarily scalars. Add vector support along with the test. llvm-svn: 301070
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@ -1391,11 +1391,14 @@ Instruction *InstCombiner::visitFAdd(BinaryOperator &I) {
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// analysis can tell us that the result of the addition has less significant
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// analysis can tell us that the result of the addition has less significant
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// bits than the integer type can hold.
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// bits than the integer type can hold.
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auto IsValidPromotion = [](Type *FTy, Type *ITy) {
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auto IsValidPromotion = [](Type *FTy, Type *ITy) {
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Type *FScalarTy = FTy->getScalarType();
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Type *IScalarTy = ITy->getScalarType();
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// Do we have enough bits in the significand to represent the result of
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// Do we have enough bits in the significand to represent the result of
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// the integer addition?
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// the integer addition?
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unsigned MaxRepresentableBits =
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unsigned MaxRepresentableBits =
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APFloat::semanticsPrecision(FTy->getFltSemantics());
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APFloat::semanticsPrecision(FScalarTy->getFltSemantics());
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return ITy->getIntegerBitWidth() <= MaxRepresentableBits;
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return IScalarTy->getIntegerBitWidth() <= MaxRepresentableBits;
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};
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};
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// (fadd double (sitofp x), fpcst) --> (sitofp (add int x, intcst))
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// (fadd double (sitofp x), fpcst) --> (sitofp (add int x, intcst))
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@ -100,3 +100,42 @@ define float @test_3(i32 %a, i32 %b) {
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%p = fadd float %o, 1.0
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%p = fadd float %o, 1.0
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ret float %p
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ret float %p
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}
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}
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define <4 x double> @test_4(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @test_4(
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; CHECK-NEXT: [[A_AND:%.*]] = and <4 x i32> [[A:%.*]], <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
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; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
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; CHECK-NEXT: [[ADDCONV:%.*]] = add nuw nsw <4 x i32> [[A_AND]], [[B_AND]]
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; CHECK-NEXT: [[RES:%.*]] = sitofp <4 x i32> [[ADDCONV]] to <4 x double>
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; CHECK-NEXT: ret <4 x double> [[RES]]
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;
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; Drop two highest bits to guarantee that %a + %b doesn't overflow
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%a_and = and <4 x i32> %a, <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
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%b_and = and <4 x i32> %b, <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
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%a_and_fp = sitofp <4 x i32> %a_and to <4 x double>
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%b_and_fp = sitofp <4 x i32> %b_and to <4 x double>
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%res = fadd <4 x double> %a_and_fp, %b_and_fp
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ret <4 x double> %res
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}
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define <4 x float> @test_4_neg(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: @test_4_neg(
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; CHECK-NEXT: [[A_AND:%.*]] = and <4 x i32> [[A:%.*]], <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
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; CHECK-NEXT: [[B_AND:%.*]] = and <4 x i32> [[B:%.*]], <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
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; CHECK-NEXT: [[A_AND_FP:%.*]] = sitofp <4 x i32> [[A_AND]] to <4 x float>
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; CHECK-NEXT: [[B_AND_FP:%.*]] = sitofp <4 x i32> [[B_AND]] to <4 x float>
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; CHECK-NEXT: [[RES:%.*]] = fadd <4 x float> [[A_AND_FP]], [[B_AND_FP]]
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; CHECK-NEXT: ret <4 x float> [[RES]]
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;
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; Drop two highest bits to guarantee that %a + %b doesn't overflow
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%a_and = and <4 x i32> %a, <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
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%b_and = and <4 x i32> %b, <i32 1073741823, i32 1073741823, i32 1073741823, i32 1073741823>
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%a_and_fp = sitofp <4 x i32> %a_and to <4 x float>
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%b_and_fp = sitofp <4 x i32> %b_and to <4 x float>
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%res = fadd <4 x float> %a_and_fp, %b_and_fp
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ret <4 x float> %res
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}
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