forked from OSchip/llvm-project
[CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case) (try 2)
Summary: I'm submitting a new revision since i don't understand how to reclaim/reopen/take over the existing one, D50222. There is no such action in "Add Action" menu... Original patch D50222 by @hermord (Dmytro Shynkevych) This implements an optimization described in Hacker's Delight 10-17: when `C` is constant, the result of `X % C == 0` can be computed more cheaply without actually calculating the remainder. The motivation is discussed here: https://bugs.llvm.org/show_bug.cgi?id=35479. Original patch author: @hermord (Dmytro Shynkevych)! Notes: - In principle, it's possible to also handle the `X % C1 == C2` case, as discussed on bugzilla. This seems to require an extra branch on overflow, so I refrained from implementing this for now. - An explicit check for when the `REM` can be reduced to just its LHS is included: the `X % C` == 0 optimization breaks `test1` in `test/CodeGen/X86/jump_sign.ll` otherwise. I hadn't managed to find a better way to not generate worse output in this case. - The `test/CodeGen/X86/jump_sign.ll` regresses, and is being fixed by a followup patch D63390. Reviewers: RKSimon, craig.topper, spatel, hermord, xbolva00 Reviewed By: RKSimon, xbolva00 Subscribers: xbolva00, javed.absar, llvm-commits, hermord Tags: #llvm Differential Revision: https://reviews.llvm.org/D63391 llvm-svn: 364563
This commit is contained in:
Roman Lebedev
parent
3b4a667854
commit
0627b09863
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@ -4054,6 +4054,12 @@ private:
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SDValue N1, ISD::CondCode Cond,
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DAGCombinerInfo &DCI,
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const SDLoc &DL) const;
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SDValue prepareUREMEqFold(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
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DAGCombinerInfo &DCI, const SDLoc &DL,
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SmallVectorImpl<SDNode *> &Created) const;
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SDValue buildUREMEqFold(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
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DAGCombinerInfo &DCI, const SDLoc &DL) const;
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};
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/// Given an LLVM IR type and return type attributes, compute the return value
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@ -3460,6 +3460,18 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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return V;
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}
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// Fold remainder of division by a constant.
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if (N0.getOpcode() == ISD::UREM && N0.hasOneUse() &&
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(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
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AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
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// When division is cheap or optimizing for minimum size,
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// fall through to DIVREM creation by skipping this fold.
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if (!isIntDivCheap(VT, Attr) && !Attr.hasFnAttribute(Attribute::MinSize))
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if (SDValue Folded = buildUREMEqFold(VT, N0, N1, Cond, DCI, dl))
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return Folded;
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}
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// Fold away ALL boolean setcc's.
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if (N0.getValueType().getScalarType() == MVT::i1 && foldBooleans) {
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SDValue Temp;
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@ -4445,6 +4457,101 @@ SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
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return DAG.getSelect(dl, VT, IsOne, N0, Q);
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}
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/// Given an ISD::UREM used only by an ISD::SETEQ or ISD::SETNE
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/// where the divisor is constant and the comparison target is zero,
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/// return a DAG expression that will generate the same comparison result
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/// using only multiplications, additions and shifts/rotations.
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/// Ref: "Hacker's Delight" 10-17.
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SDValue TargetLowering::buildUREMEqFold(EVT VT, SDValue REMNode,
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SDValue CompNode, ISD::CondCode Cond,
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DAGCombinerInfo &DCI,
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const SDLoc &DL) const {
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SmallVector<SDNode *, 2> Built;
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if (SDValue Folded =
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prepareUREMEqFold(VT, REMNode, CompNode, Cond, DCI, DL, Built)) {
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for (SDNode *N : Built)
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DCI.AddToWorklist(N);
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return Folded;
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}
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return SDValue();
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}
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SDValue
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TargetLowering::prepareUREMEqFold(EVT VT, SDValue REMNode, SDValue CompNode,
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ISD::CondCode Cond, DAGCombinerInfo &DCI,
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const SDLoc &DL,
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SmallVectorImpl<SDNode *> &Created) const {
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// fold (seteq/ne (urem N, D), 0) -> (setule/ugt (rotr (mul N, P), K), Q)
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// - D must be constant with D = D0 * 2^K where D0 is odd and D0 != 1
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// - P is the multiplicative inverse of D0 modulo 2^W
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// - Q = floor((2^W - 1) / D0)
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// where W is the width of the common type of N and D.
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assert((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
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"Only applicable for (in)equality comparisons.");
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EVT REMVT = REMNode->getValueType(0);
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// If MUL is unavailable, we cannot proceed in any case.
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if (!isOperationLegalOrCustom(ISD::MUL, REMVT))
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return SDValue();
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// TODO: Add non-uniform constant support.
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ConstantSDNode *Divisor = isConstOrConstSplat(REMNode->getOperand(1));
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ConstantSDNode *CompTarget = isConstOrConstSplat(CompNode);
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if (!Divisor || !CompTarget || Divisor->isNullValue() ||
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!CompTarget->isNullValue())
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return SDValue();
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const APInt &D = Divisor->getAPIntValue();
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// Decompose D into D0 * 2^K
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unsigned K = D.countTrailingZeros();
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bool DivisorIsEven = (K != 0);
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APInt D0 = D.lshr(K);
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// The fold is invalid when D0 == 1.
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// This is reachable because visitSetCC happens before visitREM.
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if (D0.isOneValue())
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return SDValue();
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// P = inv(D0, 2^W)
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// 2^W requires W + 1 bits, so we have to extend and then truncate.
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unsigned W = D.getBitWidth();
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APInt P = D0.zext(W + 1)
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.multiplicativeInverse(APInt::getHighBitsSet(W + 1, 1))
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.trunc(W);
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// Q = floor((2^W - 1) / D0)
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APInt Q = APInt::getAllOnesValue(W).udiv(D0);
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SelectionDAG &DAG = DCI.DAG;
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SDValue PVal = DAG.getConstant(P, DL, REMVT);
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SDValue QVal = DAG.getConstant(Q, DL, REMVT);
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// (mul N, P)
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SDValue Op1 = DAG.getNode(ISD::MUL, DL, REMVT, REMNode->getOperand(0), PVal);
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Created.push_back(Op1.getNode());
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// Rotate right only if D was even.
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if (DivisorIsEven) {
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// We need ROTR to do this.
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if (!isOperationLegalOrCustom(ISD::ROTR, REMVT))
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return SDValue();
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SDValue ShAmt =
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DAG.getConstant(K, DL, getShiftAmountTy(REMVT, DAG.getDataLayout()));
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SDNodeFlags Flags;
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Flags.setExact(true);
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// UREM: (rotr (mul N, P), K)
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Op1 = DAG.getNode(ISD::ROTR, DL, REMVT, Op1, ShAmt, Flags);
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Created.push_back(Op1.getNode());
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}
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// UREM: (setule/setugt (rotr (mul N, P), K), Q)
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return DAG.getSetCC(DL, VT, Op1, QVal,
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((Cond == ISD::SETEQ) ? ISD::SETULE : ISD::SETUGT));
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}
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bool TargetLowering::
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verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
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if (!isa<ConstantSDNode>(Op.getOperand(0))) {
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@ -26,13 +26,13 @@ define i32 @test_optsize(i32 %X) optsize nounwind readnone {
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: movk w8, #52428, lsl #16
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; CHECK-NEXT: umull x8, w0, w8
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; CHECK-NEXT: lsr x8, x8, #34
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; CHECK-NEXT: add w8, w8, w8, lsl #2
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; CHECK-NEXT: mov w9, #-10
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; CHECK-NEXT: cmp w0, w8
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; CHECK-NEXT: mov w9, #13108
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; CHECK-NEXT: movk w9, #13107, lsl #16
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; CHECK-NEXT: mul w8, w0, w8
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; CHECK-NEXT: mov w10, #-10
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: mov w8, #42
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; CHECK-NEXT: csel w0, w8, w9, eq
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; CHECK-NEXT: csel w0, w8, w10, lo
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; CHECK-NEXT: ret
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%rem = urem i32 %X, 5
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%cmp = icmp eq i32 %rem, 0
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@ -9,13 +9,9 @@ define <4 x i32> @test_urem_odd_vec_i32(<4 x i32> %X) nounwind readnone {
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: movk w8, #52428, lsl #16
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; CHECK-NEXT: dup v2.4s, w8
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; CHECK-NEXT: umull2 v3.2d, v0.4s, v2.4s
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; CHECK-NEXT: umull v2.2d, v0.2s, v2.2s
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; CHECK-NEXT: uzp2 v2.4s, v2.4s, v3.4s
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; CHECK-NEXT: movi v1.4s, #5
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; CHECK-NEXT: ushr v2.4s, v2.4s, #2
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; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s
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; CHECK-NEXT: cmeq v0.4s, v0.4s, #0
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; CHECK-NEXT: movi v1.16b, #51
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; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: movi v1.4s, #1
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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@ -31,13 +27,9 @@ define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone {
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: dup v2.8h, w8
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; CHECK-NEXT: umull2 v3.4s, v0.8h, v2.8h
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; CHECK-NEXT: umull v2.4s, v0.4h, v2.4h
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; CHECK-NEXT: uzp2 v2.8h, v2.8h, v3.8h
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; CHECK-NEXT: movi v1.8h, #5
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; CHECK-NEXT: ushr v2.8h, v2.8h, #2
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; CHECK-NEXT: mls v0.8h, v2.8h, v1.8h
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; CHECK-NEXT: cmeq v0.8h, v0.8h, #0
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; CHECK-NEXT: movi v1.16b, #51
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; CHECK-NEXT: mul v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: cmhs v0.8h, v1.8h, v0.8h
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; CHECK-NEXT: movi v1.8h, #1
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; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
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; CHECK-NEXT: ret
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@ -10,11 +10,11 @@ define i32 @test_urem_odd(i32 %X) nounwind readnone {
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #52429
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; CHECK-NEXT: movk w8, #52428, lsl #16
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; CHECK-NEXT: umull x8, w0, w8
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; CHECK-NEXT: lsr x8, x8, #34
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; CHECK-NEXT: add w8, w8, w8, lsl #2
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; CHECK-NEXT: cmp w0, w8
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: mov w9, #13108
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; CHECK-NEXT: mul w8, w0, w8
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; CHECK-NEXT: movk w9, #13107, lsl #16
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 5
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%cmp = icmp eq i32 %urem, 0
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@ -26,14 +26,11 @@ define i32 @test_urem_odd(i32 %X) nounwind readnone {
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define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone {
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; CHECK-LABEL: test_urem_odd_bit30:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-11
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; CHECK-NEXT: umull x8, w0, w8
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; CHECK-NEXT: mov w9, #3
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; CHECK-NEXT: lsr x8, x8, #62
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; CHECK-NEXT: movk w9, #16384, lsl #16
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; CHECK-NEXT: msub w8, w8, w9, w0
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #27306, lsl #16
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; CHECK-NEXT: mul w8, w0, w8
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; CHECK-NEXT: cmp w8, #4 // =4
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 1073741827
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%cmp = icmp eq i32 %urem, 0
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@ -45,14 +42,11 @@ define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone {
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define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone {
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; CHECK-LABEL: test_urem_odd_bit31:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: lsl x9, x8, #30
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; CHECK-NEXT: sub x8, x9, x8
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; CHECK-NEXT: lsr x8, x8, #61
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; CHECK-NEXT: mov w9, #-2147483645
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; CHECK-NEXT: msub w8, w8, w9, w0
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: mov w8, #43691
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; CHECK-NEXT: movk w8, #10922, lsl #16
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; CHECK-NEXT: mul w8, w0, w8
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; CHECK-NEXT: cmp w8, #2 // =2
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 2147483651
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%cmp = icmp eq i32 %urem, 0
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@ -69,16 +63,15 @@ define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone {
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define i16 @test_urem_even(i16 %X) nounwind readnone {
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; CHECK-LABEL: test_urem_even:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w10, #9363
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; CHECK-NEXT: ubfx w9, w0, #1, #15
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; CHECK-NEXT: movk w10, #37449, lsl #16
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; CHECK-NEXT: umull x9, w9, w10
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; CHECK-NEXT: mov w9, #28087
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; CHECK-NEXT: and w8, w0, #0xffff
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; CHECK-NEXT: lsr x9, x9, #34
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; CHECK-NEXT: mov w10, #14
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; CHECK-NEXT: msub w8, w9, w10, w8
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: movk w9, #46811, lsl #16
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; CHECK-NEXT: mul w8, w8, w9
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; CHECK-NEXT: mov w9, #18724
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; CHECK-NEXT: ror w8, w8, #1
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; CHECK-NEXT: movk w9, #9362, lsl #16
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; CHECK-NEXT: cmp w8, w9
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; CHECK-NEXT: cset w0, hi
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; CHECK-NEXT: ret
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%urem = urem i16 %X, 14
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%cmp = icmp ne i16 %urem, 0
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@ -90,14 +83,12 @@ define i16 @test_urem_even(i16 %X) nounwind readnone {
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define i32 @test_urem_even_bit30(i32 %X) nounwind readnone {
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; CHECK-LABEL: test_urem_even_bit30:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #-415
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; CHECK-NEXT: umull x8, w0, w8
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; CHECK-NEXT: mov w9, #104
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; CHECK-NEXT: lsr x8, x8, #62
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; CHECK-NEXT: movk w9, #16384, lsl #16
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; CHECK-NEXT: msub w8, w8, w9, w0
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: mov w8, #20165
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; CHECK-NEXT: movk w8, #64748, lsl #16
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; CHECK-NEXT: mul w8, w0, w8
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; CHECK-NEXT: ror w8, w8, #3
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; CHECK-NEXT: cmp w8, #32 // =32
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 1073741928
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%cmp = icmp eq i32 %urem, 0
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@ -109,15 +100,12 @@ define i32 @test_urem_even_bit30(i32 %X) nounwind readnone {
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define i32 @test_urem_even_bit31(i32 %X) nounwind readnone {
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; CHECK-LABEL: test_urem_even_bit31:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #65435
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; CHECK-NEXT: movk w8, #32767, lsl #16
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; CHECK-NEXT: umull x8, w0, w8
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; CHECK-NEXT: mov w9, #102
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; CHECK-NEXT: lsr x8, x8, #62
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; CHECK-NEXT: movk w9, #32768, lsl #16
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; CHECK-NEXT: msub w8, w8, w9, w0
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; CHECK-NEXT: cmp w8, #0 // =0
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: mov w8, #64251
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; CHECK-NEXT: movk w8, #47866, lsl #16
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; CHECK-NEXT: mul w8, w0, w8
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; CHECK-NEXT: ror w8, w8, #1
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; CHECK-NEXT: cmp w8, #4 // =4
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; CHECK-NEXT: cset w0, lo
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; CHECK-NEXT: ret
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%urem = urem i32 %X, 2147483750
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%cmp = icmp eq i32 %urem, 0
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@ -236,13 +236,11 @@ define void @func_o() nounwind uwtable {
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; CHECK-NEXT: jne .LBB12_8
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; CHECK-NEXT: # %bb.4: # %if.end29
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; CHECK-NEXT: movzwl (%eax), %eax
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; CHECK-NEXT: imull $-13107, %eax, %eax # imm = 0xCCCD
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; CHECK-NEXT: rorw %ax
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: imull $52429, %eax, %ecx # imm = 0xCCCD
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; CHECK-NEXT: shrl $18, %ecx
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; CHECK-NEXT: andl $-2, %ecx
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; CHECK-NEXT: leal (%ecx,%ecx,4), %ecx
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; CHECK-NEXT: cmpw %cx, %ax
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; CHECK-NEXT: jne .LBB12_5
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; CHECK-NEXT: cmpl $13108, %eax # imm = 0x3334
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; CHECK-NEXT: jae .LBB12_5
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; CHECK-NEXT: .LBB12_8: # %if.then44
|
||||
; CHECK-NEXT: xorl %eax, %eax
|
||||
; CHECK-NEXT: testb %al, %al
|
||||
|
|
|
|||
|
|
@ -40,16 +40,12 @@ define i1 @p2_scalar_shifted_urem_by_const(i32 %x, i32 %y) {
|
|||
; CHECK-LABEL: p2_scalar_shifted_urem_by_const:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: movl %esi, %ecx
|
||||
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; CHECK-NEXT: andl $1, %edi
|
||||
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
|
||||
; CHECK-NEXT: shll %cl, %edi
|
||||
; CHECK-NEXT: movl $2863311531, %eax # imm = 0xAAAAAAAB
|
||||
; CHECK-NEXT: imulq %rdi, %rax
|
||||
; CHECK-NEXT: shrq $33, %rax
|
||||
; CHECK-NEXT: leal (%rax,%rax,2), %eax
|
||||
; CHECK-NEXT: cmpl %eax, %edi
|
||||
; CHECK-NEXT: sete %al
|
||||
; CHECK-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
|
||||
; CHECK-NEXT: cmpl $1431655766, %eax # imm = 0x55555556
|
||||
; CHECK-NEXT: setb %al
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = and i32 %x, 1 ; clearly a power-of-two or zero
|
||||
%t1 = shl i32 %t0, %y ; will still be a power-of-two or zero with any %y
|
||||
|
|
@ -62,16 +58,12 @@ define i1 @p3_scalar_shifted2_urem_by_const(i32 %x, i32 %y) {
|
|||
; CHECK-LABEL: p3_scalar_shifted2_urem_by_const:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: movl %esi, %ecx
|
||||
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; CHECK-NEXT: andl $2, %edi
|
||||
; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
|
||||
; CHECK-NEXT: shll %cl, %edi
|
||||
; CHECK-NEXT: movl $2863311531, %eax # imm = 0xAAAAAAAB
|
||||
; CHECK-NEXT: imulq %rdi, %rax
|
||||
; CHECK-NEXT: shrq $33, %rax
|
||||
; CHECK-NEXT: leal (%rax,%rax,2), %eax
|
||||
; CHECK-NEXT: cmpl %eax, %edi
|
||||
; CHECK-NEXT: sete %al
|
||||
; CHECK-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
|
||||
; CHECK-NEXT: cmpl $1431655766, %eax # imm = 0x55555556
|
||||
; CHECK-NEXT: setb %al
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = and i32 %x, 2 ; clearly a power-of-two or zero
|
||||
%t1 = shl i32 %t0, %y ; will still be a power-of-two or zero with any %y
|
||||
|
|
@ -210,14 +202,10 @@ define <4 x i1> @p8_vector_urem_by_const__nonsplat_undef3(<4 x i32> %x, <4 x i32
|
|||
define i1 @n0_urem_of_maybe_not_power_of_two(i32 %x, i32 %y) {
|
||||
; CHECK-LABEL: n0_urem_of_maybe_not_power_of_two:
|
||||
; CHECK: # %bb.0:
|
||||
; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
|
||||
; CHECK-NEXT: andl $3, %edi
|
||||
; CHECK-NEXT: movl $2863311531, %eax # imm = 0xAAAAAAAB
|
||||
; CHECK-NEXT: imulq %rdi, %rax
|
||||
; CHECK-NEXT: shrq $33, %rax
|
||||
; CHECK-NEXT: leal (%rax,%rax,2), %eax
|
||||
; CHECK-NEXT: cmpl %eax, %edi
|
||||
; CHECK-NEXT: sete %al
|
||||
; CHECK-NEXT: imull $-1431655765, %edi, %eax # imm = 0xAAAAAAAB
|
||||
; CHECK-NEXT: cmpl $1431655766, %eax # imm = 0x55555556
|
||||
; CHECK-NEXT: setb %al
|
||||
; CHECK-NEXT: retq
|
||||
%t0 = and i32 %x, 3 ; up to two bits set, not power-of-two
|
||||
%t1 = urem i32 %t0, 3
|
||||
|
|
|
|||
|
|
@ -47,15 +47,10 @@ define i32 @test_minsize(i32 %X) optsize minsize nounwind readnone {
|
|||
define i32 @test_optsize(i32 %X) optsize nounwind readnone {
|
||||
; X86-LABEL: test_optsize:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl $-858993459, %edx # imm = 0xCCCCCCCD
|
||||
; X86-NEXT: movl %ecx, %eax
|
||||
; X86-NEXT: mull %edx
|
||||
; X86-NEXT: shrl $2, %edx
|
||||
; X86-NEXT: leal (%edx,%edx,4), %eax
|
||||
; X86-NEXT: cmpl %eax, %ecx
|
||||
; X86-NEXT: imull $-858993459, {{[0-9]+}}(%esp), %eax # imm = 0xCCCCCCCD
|
||||
; X86-NEXT: cmpl $858993460, %eax # imm = 0x33333334
|
||||
; X86-NEXT: movl $42, %eax
|
||||
; X86-NEXT: je .LBB1_2
|
||||
; X86-NEXT: jb .LBB1_2
|
||||
; X86-NEXT: # %bb.1:
|
||||
; X86-NEXT: movl $-10, %eax
|
||||
; X86-NEXT: .LBB1_2:
|
||||
|
|
@ -63,15 +58,11 @@ define i32 @test_optsize(i32 %X) optsize nounwind readnone {
|
|||
;
|
||||
; X64-LABEL: test_optsize:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: movl $3435973837, %ecx # imm = 0xCCCCCCCD
|
||||
; X64-NEXT: imulq %rax, %rcx
|
||||
; X64-NEXT: shrq $34, %rcx
|
||||
; X64-NEXT: leal (%rcx,%rcx,4), %eax
|
||||
; X64-NEXT: cmpl %eax, %edi
|
||||
; X64-NEXT: imull $-858993459, %edi, %eax # imm = 0xCCCCCCCD
|
||||
; X64-NEXT: cmpl $858993460, %eax # imm = 0x33333334
|
||||
; X64-NEXT: movl $42, %ecx
|
||||
; X64-NEXT: movl $-10, %eax
|
||||
; X64-NEXT: cmovel %ecx, %eax
|
||||
; X64-NEXT: cmovbl %ecx, %eax
|
||||
; X64-NEXT: retq
|
||||
%rem = urem i32 %X, 5
|
||||
%cmp = icmp eq i32 %rem, 0
|
||||
|
|
|
|||
|
|
@ -11,84 +11,48 @@ define <4 x i32> @test_urem_odd_vec_i32(<4 x i32> %X) nounwind readnone {
|
|||
; CHECK-SSE2-LABEL: test_urem_odd_vec_i32:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837]
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm0, %xmm2
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm2
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,3,2,3]
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE2-NEXT: pmuludq %xmm1, %xmm3
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm3[1,3,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: psrld $2, %xmm2
|
||||
; CHECK-SSE2-NEXT: movdqa %xmm2, %xmm1
|
||||
; CHECK-SSE2-NEXT: pslld $2, %xmm1
|
||||
; CHECK-SSE2-NEXT: paddd %xmm2, %xmm1
|
||||
; CHECK-SSE2-NEXT: psubd %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-SSE2-NEXT: pcmpeqd %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: psrld $31, %xmm0
|
||||
; CHECK-SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm2[0,2,2,3]
|
||||
; CHECK-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
|
||||
; CHECK-SSE2-NEXT: pxor {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pcmpgtd {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pandn {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE41-LABEL: test_urem_odd_vec_i32:
|
||||
; CHECK-SSE41: # %bb.0:
|
||||
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837]
|
||||
; CHECK-SSE41-NEXT: pmuludq %xmm2, %xmm1
|
||||
; CHECK-SSE41-NEXT: pmuludq %xmm0, %xmm2
|
||||
; CHECK-SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
||||
; CHECK-SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
|
||||
; CHECK-SSE41-NEXT: psrld $2, %xmm2
|
||||
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm2
|
||||
; CHECK-SSE41-NEXT: psubd %xmm2, %xmm0
|
||||
; CHECK-SSE41-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-SSE41-NEXT: pmulld {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [858993459,858993459,858993459,858993459]
|
||||
; CHECK-SSE41-NEXT: pminud %xmm0, %xmm1
|
||||
; CHECK-SSE41-NEXT: pcmpeqd %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: psrld $31, %xmm0
|
||||
; CHECK-SSE41-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX1-LABEL: test_urem_odd_vec_i32:
|
||||
; CHECK-AVX1: # %bb.0:
|
||||
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837]
|
||||
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
|
||||
; CHECK-AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
||||
; CHECK-AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
|
||||
; CHECK-AVX1-NEXT: vpsrld $2, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpminud {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX1-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: vpsrld $31, %xmm0, %xmm0
|
||||
; CHECK-AVX1-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX2-LABEL: test_urem_odd_vec_i32:
|
||||
; CHECK-AVX2: # %bb.0:
|
||||
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837]
|
||||
; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
|
||||
; CHECK-AVX2-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
||||
; CHECK-AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
|
||||
; CHECK-AVX2-NEXT: vpsrld $2, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [5,5,5,5]
|
||||
; CHECK-AVX2-NEXT: vpmulld %xmm2, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3435973837,3435973837,3435973837,3435973837]
|
||||
; CHECK-AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm1 = [858993459,858993459,858993459,858993459]
|
||||
; CHECK-AVX2-NEXT: vpminud %xmm1, %xmm0, %xmm1
|
||||
; CHECK-AVX2-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: vpsrld $31, %xmm0, %xmm0
|
||||
; CHECK-AVX2-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX512VL-LABEL: test_urem_odd_vec_i32:
|
||||
; CHECK-AVX512VL: # %bb.0:
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm0[1,1,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm2 = [3435973837,3435973837,3435973837,3435973837]
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm2, %xmm0, %xmm2
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm2[0],xmm1[1],xmm2[2],xmm1[3]
|
||||
; CHECK-AVX512VL-NEXT: vpsrld $2, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: retq
|
||||
|
|
@ -100,25 +64,28 @@ define <4 x i32> @test_urem_odd_vec_i32(<4 x i32> %X) nounwind readnone {
|
|||
|
||||
; Like test_urem_odd_vec_i32, but with 8 x i16 vectors.
|
||||
define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone {
|
||||
; CHECK-SSE-LABEL: test_urem_odd_vec_i16:
|
||||
; CHECK-SSE: # %bb.0:
|
||||
; CHECK-SSE-NEXT: movdqa {{.*#+}} xmm1 = [52429,52429,52429,52429,52429,52429,52429,52429]
|
||||
; CHECK-SSE-NEXT: pmulhuw %xmm0, %xmm1
|
||||
; CHECK-SSE-NEXT: psrlw $2, %xmm1
|
||||
; CHECK-SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
|
||||
; CHECK-SSE-NEXT: psubw %xmm1, %xmm0
|
||||
; CHECK-SSE-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-SSE-NEXT: pcmpeqw %xmm1, %xmm0
|
||||
; CHECK-SSE-NEXT: psrlw $15, %xmm0
|
||||
; CHECK-SSE-NEXT: retq
|
||||
; CHECK-SSE2-LABEL: test_urem_odd_vec_i16:
|
||||
; CHECK-SSE2: # %bb.0:
|
||||
; CHECK-SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: psubusw {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE2-NEXT: pxor %xmm1, %xmm1
|
||||
; CHECK-SSE2-NEXT: pcmpeqw %xmm1, %xmm0
|
||||
; CHECK-SSE2-NEXT: psrlw $15, %xmm0
|
||||
; CHECK-SSE2-NEXT: retq
|
||||
;
|
||||
; CHECK-SSE41-LABEL: test_urem_odd_vec_i16:
|
||||
; CHECK-SSE41: # %bb.0:
|
||||
; CHECK-SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0
|
||||
; CHECK-SSE41-NEXT: movdqa {{.*#+}} xmm1 = [13107,13107,13107,13107,13107,13107,13107,13107]
|
||||
; CHECK-SSE41-NEXT: pminuw %xmm0, %xmm1
|
||||
; CHECK-SSE41-NEXT: pcmpeqw %xmm1, %xmm0
|
||||
; CHECK-SSE41-NEXT: psrlw $15, %xmm0
|
||||
; CHECK-SSE41-NEXT: retq
|
||||
;
|
||||
; CHECK-AVX-LABEL: test_urem_odd_vec_i16:
|
||||
; CHECK-AVX: # %bb.0:
|
||||
; CHECK-AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX-NEXT: vpsrlw $2, %xmm1, %xmm1
|
||||
; CHECK-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
|
||||
; CHECK-AVX-NEXT: vpsubw %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vpminuw {{.*}}(%rip), %xmm0, %xmm1
|
||||
; CHECK-AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: vpsrlw $15, %xmm0, %xmm0
|
||||
; CHECK-AVX-NEXT: retq
|
||||
|
|
@ -214,17 +181,9 @@ define <4 x i32> @test_urem_even_vec_i32(<4 x i32> %X) nounwind readnone {
|
|||
;
|
||||
; CHECK-AVX512VL-LABEL: test_urem_even_vec_i32:
|
||||
; CHECK-AVX512VL: # %bb.0:
|
||||
; CHECK-AVX512VL-NEXT: vpsrld $1, %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpbroadcastd {{.*#+}} xmm3 = [2454267027,2454267027,2454267027,2454267027]
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm3, %xmm2, %xmm2
|
||||
; CHECK-AVX512VL-NEXT: vpmuludq %xmm3, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]
|
||||
; CHECK-AVX512VL-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2],xmm2[3]
|
||||
; CHECK-AVX512VL-NEXT: vpsrld $2, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpsubd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpxor %xmm1, %xmm1, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpmulld {{.*}}(%rip){1to4}, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vprord $1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpminud {{.*}}(%rip){1to4}, %xmm0, %xmm1
|
||||
; CHECK-AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: vpsrld $31, %xmm0, %xmm0
|
||||
; CHECK-AVX512VL-NEXT: retq
|
||||
|
|
|
|||
|
|
@ -9,27 +9,18 @@
|
|||
define i32 @test_urem_odd(i32 %X) nounwind readnone {
|
||||
; X86-LABEL: test_urem_odd:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl $-858993459, %edx # imm = 0xCCCCCCCD
|
||||
; X86-NEXT: movl %ecx, %eax
|
||||
; X86-NEXT: mull %edx
|
||||
; X86-NEXT: shrl $2, %edx
|
||||
; X86-NEXT: leal (%edx,%edx,4), %edx
|
||||
; X86-NEXT: imull $-858993459, {{[0-9]+}}(%esp), %ecx # imm = 0xCCCCCCCD
|
||||
; X86-NEXT: xorl %eax, %eax
|
||||
; X86-NEXT: cmpl %edx, %ecx
|
||||
; X86-NEXT: sete %al
|
||||
; X86-NEXT: cmpl $858993460, %ecx # imm = 0x33333334
|
||||
; X86-NEXT: setb %al
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_urem_odd:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: movl $3435973837, %ecx # imm = 0xCCCCCCCD
|
||||
; X64-NEXT: imulq %rax, %rcx
|
||||
; X64-NEXT: shrq $34, %rcx
|
||||
; X64-NEXT: leal (%rcx,%rcx,4), %ecx
|
||||
; X64-NEXT: imull $-858993459, %edi, %ecx # imm = 0xCCCCCCCD
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: cmpl %ecx, %edi
|
||||
; X64-NEXT: sete %al
|
||||
; X64-NEXT: cmpl $858993460, %ecx # imm = 0x33333334
|
||||
; X64-NEXT: setb %al
|
||||
; X64-NEXT: retq
|
||||
%urem = urem i32 %X, 5
|
||||
%cmp = icmp eq i32 %urem, 0
|
||||
|
|
@ -41,27 +32,18 @@ define i32 @test_urem_odd(i32 %X) nounwind readnone {
|
|||
define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone {
|
||||
; X86-LABEL: test_urem_odd_bit30:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl $-11, %edx
|
||||
; X86-NEXT: movl %ecx, %eax
|
||||
; X86-NEXT: mull %edx
|
||||
; X86-NEXT: shrl $30, %edx
|
||||
; X86-NEXT: imull $1073741827, %edx, %edx # imm = 0x40000003
|
||||
; X86-NEXT: imull $1789569707, {{[0-9]+}}(%esp), %ecx # imm = 0x6AAAAAAB
|
||||
; X86-NEXT: xorl %eax, %eax
|
||||
; X86-NEXT: cmpl %edx, %ecx
|
||||
; X86-NEXT: sete %al
|
||||
; X86-NEXT: cmpl $4, %ecx
|
||||
; X86-NEXT: setb %al
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_urem_odd_bit30:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: movl $4294967285, %ecx # imm = 0xFFFFFFF5
|
||||
; X64-NEXT: imulq %rax, %rcx
|
||||
; X64-NEXT: shrq $62, %rcx
|
||||
; X64-NEXT: imull $1073741827, %ecx, %ecx # imm = 0x40000003
|
||||
; X64-NEXT: imull $1789569707, %edi, %ecx # imm = 0x6AAAAAAB
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: cmpl %ecx, %edi
|
||||
; X64-NEXT: sete %al
|
||||
; X64-NEXT: cmpl $4, %ecx
|
||||
; X64-NEXT: setb %al
|
||||
; X64-NEXT: retq
|
||||
%urem = urem i32 %X, 1073741827
|
||||
%cmp = icmp eq i32 %urem, 0
|
||||
|
|
@ -73,28 +55,18 @@ define i32 @test_urem_odd_bit30(i32 %X) nounwind readnone {
|
|||
define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone {
|
||||
; X86-LABEL: test_urem_odd_bit31:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl $1073741823, %edx # imm = 0x3FFFFFFF
|
||||
; X86-NEXT: movl %ecx, %eax
|
||||
; X86-NEXT: mull %edx
|
||||
; X86-NEXT: shrl $29, %edx
|
||||
; X86-NEXT: imull $-2147483645, %edx, %edx # imm = 0x80000003
|
||||
; X86-NEXT: imull $715827883, {{[0-9]+}}(%esp), %ecx # imm = 0x2AAAAAAB
|
||||
; X86-NEXT: xorl %eax, %eax
|
||||
; X86-NEXT: cmpl %edx, %ecx
|
||||
; X86-NEXT: sete %al
|
||||
; X86-NEXT: cmpl $2, %ecx
|
||||
; X86-NEXT: setb %al
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_urem_odd_bit31:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: movq %rax, %rcx
|
||||
; X64-NEXT: shlq $30, %rcx
|
||||
; X64-NEXT: subq %rax, %rcx
|
||||
; X64-NEXT: shrq $61, %rcx
|
||||
; X64-NEXT: imull $-2147483645, %ecx, %ecx # imm = 0x80000003
|
||||
; X64-NEXT: imull $715827883, %edi, %ecx # imm = 0x2AAAAAAB
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: cmpl %ecx, %edi
|
||||
; X64-NEXT: sete %al
|
||||
; X64-NEXT: cmpl $2, %ecx
|
||||
; X64-NEXT: setb %al
|
||||
; X64-NEXT: retq
|
||||
%urem = urem i32 %X, 2147483651
|
||||
%cmp = icmp eq i32 %urem, 0
|
||||
|
|
@ -111,35 +83,23 @@ define i32 @test_urem_odd_bit31(i32 %X) nounwind readnone {
|
|||
define i16 @test_urem_even(i16 %X) nounwind readnone {
|
||||
; X86-LABEL: test_urem_even:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl %ecx, %eax
|
||||
; X86-NEXT: shrl %eax
|
||||
; X86-NEXT: imull $18725, %eax, %eax # imm = 0x4925
|
||||
; X86-NEXT: shrl $17, %eax
|
||||
; X86-NEXT: movl %eax, %edx
|
||||
; X86-NEXT: shll $4, %edx
|
||||
; X86-NEXT: subl %eax, %edx
|
||||
; X86-NEXT: subl %eax, %edx
|
||||
; X86-NEXT: imull $28087, {{[0-9]+}}(%esp), %eax # imm = 0x6DB7
|
||||
; X86-NEXT: rorw %ax
|
||||
; X86-NEXT: movzwl %ax, %ecx
|
||||
; X86-NEXT: xorl %eax, %eax
|
||||
; X86-NEXT: cmpw %dx, %cx
|
||||
; X86-NEXT: setne %al
|
||||
; X86-NEXT: cmpl $9362, %ecx # imm = 0x2492
|
||||
; X86-NEXT: seta %al
|
||||
; X86-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_urem_even:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movzwl %di, %ecx
|
||||
; X64-NEXT: movl %ecx, %eax
|
||||
; X64-NEXT: shrl %eax
|
||||
; X64-NEXT: imull $18725, %eax, %eax # imm = 0x4925
|
||||
; X64-NEXT: shrl $17, %eax
|
||||
; X64-NEXT: movl %eax, %edx
|
||||
; X64-NEXT: shll $4, %edx
|
||||
; X64-NEXT: subl %eax, %edx
|
||||
; X64-NEXT: subl %eax, %edx
|
||||
; X64-NEXT: imull $28087, %edi, %eax # imm = 0x6DB7
|
||||
; X64-NEXT: rorw %ax
|
||||
; X64-NEXT: movzwl %ax, %ecx
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: cmpw %dx, %cx
|
||||
; X64-NEXT: setne %al
|
||||
; X64-NEXT: cmpl $9362, %ecx # imm = 0x2492
|
||||
; X64-NEXT: seta %al
|
||||
; X64-NEXT: # kill: def $ax killed $ax killed $eax
|
||||
; X64-NEXT: retq
|
||||
%urem = urem i16 %X, 14
|
||||
|
|
@ -152,27 +112,20 @@ define i16 @test_urem_even(i16 %X) nounwind readnone {
|
|||
define i32 @test_urem_even_bit30(i32 %X) nounwind readnone {
|
||||
; X86-LABEL: test_urem_even_bit30:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl $-415, %edx # imm = 0xFE61
|
||||
; X86-NEXT: movl %ecx, %eax
|
||||
; X86-NEXT: mull %edx
|
||||
; X86-NEXT: shrl $30, %edx
|
||||
; X86-NEXT: imull $1073741928, %edx, %edx # imm = 0x40000068
|
||||
; X86-NEXT: imull $-51622203, {{[0-9]+}}(%esp), %ecx # imm = 0xFCEC4EC5
|
||||
; X86-NEXT: rorl $3, %ecx
|
||||
; X86-NEXT: xorl %eax, %eax
|
||||
; X86-NEXT: cmpl %edx, %ecx
|
||||
; X86-NEXT: sete %al
|
||||
; X86-NEXT: cmpl $32, %ecx
|
||||
; X86-NEXT: setb %al
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_urem_even_bit30:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: movl $4294966881, %ecx # imm = 0xFFFFFE61
|
||||
; X64-NEXT: imulq %rax, %rcx
|
||||
; X64-NEXT: shrq $62, %rcx
|
||||
; X64-NEXT: imull $1073741928, %ecx, %ecx # imm = 0x40000068
|
||||
; X64-NEXT: imull $-51622203, %edi, %ecx # imm = 0xFCEC4EC5
|
||||
; X64-NEXT: rorl $3, %ecx
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: cmpl %ecx, %edi
|
||||
; X64-NEXT: sete %al
|
||||
; X64-NEXT: cmpl $32, %ecx
|
||||
; X64-NEXT: setb %al
|
||||
; X64-NEXT: retq
|
||||
%urem = urem i32 %X, 1073741928
|
||||
%cmp = icmp eq i32 %urem, 0
|
||||
|
|
@ -184,26 +137,20 @@ define i32 @test_urem_even_bit30(i32 %X) nounwind readnone {
|
|||
define i32 @test_urem_even_bit31(i32 %X) nounwind readnone {
|
||||
; X86-LABEL: test_urem_even_bit31:
|
||||
; X86: # %bb.0:
|
||||
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
||||
; X86-NEXT: movl $2147483547, %edx # imm = 0x7FFFFF9B
|
||||
; X86-NEXT: movl %ecx, %eax
|
||||
; X86-NEXT: mull %edx
|
||||
; X86-NEXT: shrl $30, %edx
|
||||
; X86-NEXT: imull $-2147483546, %edx, %edx # imm = 0x80000066
|
||||
; X86-NEXT: imull $-1157956869, {{[0-9]+}}(%esp), %ecx # imm = 0xBAFAFAFB
|
||||
; X86-NEXT: rorl %ecx
|
||||
; X86-NEXT: xorl %eax, %eax
|
||||
; X86-NEXT: cmpl %edx, %ecx
|
||||
; X86-NEXT: sete %al
|
||||
; X86-NEXT: cmpl $4, %ecx
|
||||
; X86-NEXT: setb %al
|
||||
; X86-NEXT: retl
|
||||
;
|
||||
; X64-LABEL: test_urem_even_bit31:
|
||||
; X64: # %bb.0:
|
||||
; X64-NEXT: movl %edi, %eax
|
||||
; X64-NEXT: imulq $2147483547, %rax, %rax # imm = 0x7FFFFF9B
|
||||
; X64-NEXT: shrq $62, %rax
|
||||
; X64-NEXT: imull $-2147483546, %eax, %ecx # imm = 0x80000066
|
||||
; X64-NEXT: imull $-1157956869, %edi, %ecx # imm = 0xBAFAFAFB
|
||||
; X64-NEXT: rorl %ecx
|
||||
; X64-NEXT: xorl %eax, %eax
|
||||
; X64-NEXT: cmpl %ecx, %edi
|
||||
; X64-NEXT: sete %al
|
||||
; X64-NEXT: cmpl $4, %ecx
|
||||
; X64-NEXT: setb %al
|
||||
; X64-NEXT: retq
|
||||
%urem = urem i32 %X, 2147483750
|
||||
%cmp = icmp eq i32 %urem, 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue