From 06234f758e1945084582cf80450b396f75a9c06e Mon Sep 17 00:00:00 2001
From: Krzysztof Parzyszek <kparzysz@quicinc.com>
Date: Thu, 22 Apr 2021 16:18:39 -0500
Subject: [PATCH] [Hexagon] Improve lowering of returns of i1

Emit explicit any-extend to avoid weird tstbit sequences.
---
 .../Target/Hexagon/HexagonISelLowering.cpp    | 23 +++++++-
 llvm/test/CodeGen/Hexagon/isel/logical.ll     | 54 +++----------------
 llvm/test/CodeGen/Hexagon/predicate-copy.ll   | 21 +++++---
 llvm/test/MC/Hexagon/inst_cmp_eq.ll           |  9 ++--
 llvm/test/MC/Hexagon/inst_cmp_eqi.ll          |  9 ++--
 llvm/test/MC/Hexagon/inst_cmp_gt.ll           | 11 ++--
 llvm/test/MC/Hexagon/inst_cmp_gti.ll          |  9 ++--
 llvm/test/MC/Hexagon/inst_cmp_lt.ll           |  9 ++--
 llvm/test/MC/Hexagon/inst_cmp_ugt.ll          |  9 ++--
 llvm/test/MC/Hexagon/inst_cmp_ugti.ll         |  9 ++--
 llvm/test/MC/Hexagon/inst_cmp_ult.ll          |  9 ++--
 11 files changed, 76 insertions(+), 96 deletions(-)

diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 153c7e9d9489..edb8d7f26632 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -219,8 +219,29 @@ HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
   // Copy the result values into the output registers.
   for (unsigned i = 0; i != RVLocs.size(); ++i) {
     CCValAssign &VA = RVLocs[i];
+    SDValue Val = OutVals[i];
 
-    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
+    switch (VA.getLocInfo()) {
+      default:
+        // Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
+        llvm_unreachable("Unknown loc info!");
+      case CCValAssign::Full:
+        break;
+      case CCValAssign::BCvt:
+        Val = DAG.getBitcast(VA.getLocVT(), Val);
+        break;
+      case CCValAssign::SExt:
+        Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val);
+        break;
+      case CCValAssign::ZExt:
+        Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val);
+        break;
+      case CCValAssign::AExt:
+        Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val);
+        break;
+    }
+
+    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Flag);
 
     // Guarantee that all emitted copies are stuck together with flags.
     Flag = Chain.getValue(1);
diff --git a/llvm/test/CodeGen/Hexagon/isel/logical.ll b/llvm/test/CodeGen/Hexagon/isel/logical.ll
index 6c6ac7e413d6..987fb02fdb29 100644
--- a/llvm/test/CodeGen/Hexagon/isel/logical.ll
+++ b/llvm/test/CodeGen/Hexagon/isel/logical.ll
@@ -16,12 +16,6 @@ define i1 @f0(i32 %a0, i32 %a1) #1 {
 ; CHECK-NEXT:     p0 = and(p0,p1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = p0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = tstbit(r2,#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = p0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
@@ -49,12 +43,6 @@ define i1 @f1(i32 %a0, i32 %a1) #1 {
 ; CHECK-NEXT:     p0 = or(p0,p1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = p0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = tstbit(r2,#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = p0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
@@ -82,12 +70,6 @@ define i1 @f2(i32 %a0, i32 %a1) #1 {
 ; CHECK-NEXT:     p0 = xor(p0,p1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = p0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = tstbit(r2,#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = p0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
@@ -127,7 +109,7 @@ define i1 @f3(i32 %a0, i32 %a1) #1 {
 ; CHECK-NEXT:     p0 = and(p0,!p1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31
@@ -167,7 +149,7 @@ define i1 @f4(i32 %a0, i32 %a1) #1 {
 ; CHECK-NEXT:     p0 = or(p0,!p1)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31
@@ -198,12 +180,6 @@ define i1 @f5(i32 %a0, i32 %a1, i32 %a2) #1 {
 ; CHECK-NEXT:     p0 = and(p2,and(p0,p1))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = p0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = tstbit(r2,#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = p0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
@@ -237,12 +213,6 @@ define i1 @f6(i32 %a0, i32 %a1, i32 %a2) #1 {
 ; CHECK-NEXT:     p0 = and(p2,or(p0,p1))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = p0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = tstbit(r2,#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = p0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
@@ -276,12 +246,6 @@ define i1 @f7(i32 %a0, i32 %a1, i32 %a2) #1 {
 ; CHECK-NEXT:     p0 = or(p2,and(p0,p1))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = p0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = tstbit(r2,#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = p0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
@@ -315,12 +279,6 @@ define i1 @f8(i32 %a0, i32 %a1, i32 %a2) #1 {
 ; CHECK-NEXT:     p0 = or(p2,or(p0,p1))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r2 = p0
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = tstbit(r2,#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
 ; CHECK-NEXT:     r0 = p0
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
@@ -372,7 +330,7 @@ define i1 @f9(i32 %a0, i32 %a1, i32 %a2) #1 {
 ; CHECK-NEXT:     p0 = and(p2,and(p0,!p1))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31
@@ -424,7 +382,7 @@ define i1 @f10(i32 %a0, i32 %a1, i32 %a2) #1 {
 ; CHECK-NEXT:     p0 = and(p2,or(p0,!p1))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31
@@ -476,7 +434,7 @@ define i1 @f11(i32 %a0, i32 %a1, i32 %a2) #1 {
 ; CHECK-NEXT:     p0 = or(p2,and(p0,!p1))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31
@@ -528,7 +486,7 @@ define i1 @f12(i32 %a0, i32 %a1, i32 %a2) #1 {
 ; CHECK-NEXT:     p0 = or(p2,or(p0,!p1))
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:     jumpr r31
diff --git a/llvm/test/CodeGen/Hexagon/predicate-copy.ll b/llvm/test/CodeGen/Hexagon/predicate-copy.ll
index 1b58ec9e7908..8939a75d9ebb 100644
--- a/llvm/test/CodeGen/Hexagon/predicate-copy.ll
+++ b/llvm/test/CodeGen/Hexagon/predicate-copy.ll
@@ -1,10 +1,19 @@
-; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -march=hexagon < %s | FileCheck %s
 
-; CHECK: r{{[0-9]+}} = p{{[0-9]+}}
-
-define i1 @f0() #0 {
+define i1 @f0(i32 %a0) #0 {
+; CHECK-LABEL: f0:
+; CHECK:       // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = cmp.eq(r0,#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#0,#1)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:    }
 b0:
-  ret i1 false
+  %v0 = icmp ne i32 %a0, 0
+  ret i1 %v0
 }
 
-attributes #0 = { nounwind "target-cpu"="hexagonv5" }
+attributes #0 = { nounwind "target-cpu"="hexagonv66" }
diff --git a/llvm/test/MC/Hexagon/inst_cmp_eq.ll b/llvm/test/MC/Hexagon/inst_cmp_eq.ll
index 5c483451d713..5ceec215ac1e 100644
--- a/llvm/test/MC/Hexagon/inst_cmp_eq.ll
+++ b/llvm/test/MC/Hexagon/inst_cmp_eq.ll
@@ -1,12 +1,11 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-objdump -d - | FileCheck %s
 
-define i1 @foo (i32 %a, i32 %b)
-{
-  %1 = icmp eq i32 %a, %b
-  ret i1 %1
+define i1 @f0(i32 %a0, i32 %a1) {
+  %v0 = icmp eq i32 %a0, %a1
+  ret i1 %v0
 }
 
 ; CHECK: p0 = cmp.eq(r0,r1)
-; CHECK: r0 = p0
+; CHECK: r0 = mux(p0,#1,#0)
 ; CHECK: jumpr r31
diff --git a/llvm/test/MC/Hexagon/inst_cmp_eqi.ll b/llvm/test/MC/Hexagon/inst_cmp_eqi.ll
index 5d8132b70bb9..1ec6af13fdad 100644
--- a/llvm/test/MC/Hexagon/inst_cmp_eqi.ll
+++ b/llvm/test/MC/Hexagon/inst_cmp_eqi.ll
@@ -1,12 +1,11 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-objdump -d - | FileCheck %s
 
-define i1 @foo (i32 %a)
-{
-  %1 = icmp eq i32 %a, 42
-  ret i1 %1
+define i1 @f0(i32 %a0) {
+  %v0 = icmp eq i32 %a0, 42
+  ret i1 %v0
 }
 
 ; CHECK: p0 = cmp.eq(r0,#42)
-; CHECK: r0 = p0
+; CHECK: r0 = mux(p0,#1,#0)
 ; CHECK: jumpr r31
diff --git a/llvm/test/MC/Hexagon/inst_cmp_gt.ll b/llvm/test/MC/Hexagon/inst_cmp_gt.ll
index 45a4e33e940f..66112406a2d5 100644
--- a/llvm/test/MC/Hexagon/inst_cmp_gt.ll
+++ b/llvm/test/MC/Hexagon/inst_cmp_gt.ll
@@ -1,12 +1,11 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-objdump -d - | FileCheck %s
 
-define i1 @foo (i32 %a, i32 %b)
-{
-  %1 = icmp sgt i32 %a, %b
-  ret i1 %1
+define i1 @f0(i32 %a0, i32 %a1) {
+  %v0 = icmp sgt i32 %a0, %a1
+  ret i1 %v0
 }
 
 ; CHECK: p0 = cmp.gt(r0,r1)
-; CHECK: r0 = p0
-; CHECK: jumpr r31 }
+; CHECK: r0 = mux(p0,#1,#0)
+; CHECK: jumpr r31
diff --git a/llvm/test/MC/Hexagon/inst_cmp_gti.ll b/llvm/test/MC/Hexagon/inst_cmp_gti.ll
index 67cdc4c909bb..fac0cac4d545 100644
--- a/llvm/test/MC/Hexagon/inst_cmp_gti.ll
+++ b/llvm/test/MC/Hexagon/inst_cmp_gti.ll
@@ -1,12 +1,11 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-objdump -d - | FileCheck %s
 
-define i1 @foo (i32 %a)
-{
-  %1 = icmp sgt i32 %a, 42
-  ret i1 %1
+define i1 @f0(i32 %a0) {
+  %v0 = icmp sgt i32 %a0, 42
+  ret i1 %v0
 }
 
 ; CHECK: p0 = cmp.gt(r0,#42)
-; CHECK: r0 = p0
+; CHECK: r0 = mux(p0,#1,#0)
 ; CHECK: jumpr r31
diff --git a/llvm/test/MC/Hexagon/inst_cmp_lt.ll b/llvm/test/MC/Hexagon/inst_cmp_lt.ll
index b19a4a676aaf..2f00660b81fa 100644
--- a/llvm/test/MC/Hexagon/inst_cmp_lt.ll
+++ b/llvm/test/MC/Hexagon/inst_cmp_lt.ll
@@ -1,12 +1,11 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-objdump -d - | FileCheck %s
 
-define i1 @foo (i32 %a, i32 %b)
-{
-  %1 = icmp slt i32 %a, %b
-  ret i1 %1
+define i1 @f0(i32 %a0, i32 %a1) {
+  %v0 = icmp slt i32 %a0, %a1
+  ret i1 %v0
 }
 
 ; CHECK: p0 = cmp.gt(r1,r0)
-; CHECK: r0 = p0
+; CHECK: r0 = mux(p0,#1,#0)
 ; CHECK: jumpr r31
diff --git a/llvm/test/MC/Hexagon/inst_cmp_ugt.ll b/llvm/test/MC/Hexagon/inst_cmp_ugt.ll
index 7af40c6ed034..893849219a9c 100644
--- a/llvm/test/MC/Hexagon/inst_cmp_ugt.ll
+++ b/llvm/test/MC/Hexagon/inst_cmp_ugt.ll
@@ -1,12 +1,11 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-objdump -d - | FileCheck %s
 
-define i1 @foo (i32 %a, i32 %b)
-{
-  %1 = icmp ugt i32 %a, %b
-  ret i1 %1
+define i1 @f0(i32 %a0, i32 %a1) {
+  %v0 = icmp ugt i32 %a0, %a1
+  ret i1 %v0
 }
 
 ; CHECK: p0 = cmp.gtu(r0,r1)
-; CHECK: r0 = p0
+; CHECK: r0 = mux(p0,#1,#0)
 ; CHECK: jumpr r31
diff --git a/llvm/test/MC/Hexagon/inst_cmp_ugti.ll b/llvm/test/MC/Hexagon/inst_cmp_ugti.ll
index 63d94e4ff87a..ba1953a4deb3 100644
--- a/llvm/test/MC/Hexagon/inst_cmp_ugti.ll
+++ b/llvm/test/MC/Hexagon/inst_cmp_ugti.ll
@@ -1,12 +1,11 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-objdump -d - | FileCheck %s
 
-define i1 @foo (i32 %a)
-{
-  %1 = icmp ugt i32 %a, 42
-  ret i1 %1
+define i1 @f0(i32 %a0) {
+  %v0 = icmp ugt i32 %a0, 42
+  ret i1 %v0
 }
 
 ; CHECK: p0 = cmp.gtu(r0,#42)
-; CHECK: r0 = p0
+; CHECK: r0 = mux(p0,#1,#0)
 ; CHECK: jumpr r31
diff --git a/llvm/test/MC/Hexagon/inst_cmp_ult.ll b/llvm/test/MC/Hexagon/inst_cmp_ult.ll
index ecda120a4598..a6df6a4008f6 100644
--- a/llvm/test/MC/Hexagon/inst_cmp_ult.ll
+++ b/llvm/test/MC/Hexagon/inst_cmp_ult.ll
@@ -1,12 +1,11 @@
 ;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
 ;; RUN: | llvm-objdump -d - | FileCheck %s
 
-define i1 @foo (i32 %a, i32 %b)
-{
-  %1 = icmp ult i32 %a, %b
-  ret i1 %1
+define i1 @f0(i32 %a0, i32 %a1) {
+  %v0 = icmp ult i32 %a0, %a1
+  ret i1 %v0
 }
 
 ; CHECK: p0 = cmp.gtu(r1,r0)
-; CHECK: r0 = p0
+; CHECK: r0 = mux(p0,#1,#0)
 ; CHECK: jumpr r31