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[Hexagon] Improve lowering of returns of i1 

Emit explicit any-extend to avoid weird tstbit sequences.
This commit is contained in:
Krzysztof Parzyszek 2021-04-22 16:18:39 -05:00
parent 907409a536
commit 06234f758e
11 changed files with 76 additions and 96 deletions
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23
llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
View File

@ -219,8 +219,29 @@ HexagonTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
// Copy the result values into the output registers.
for (unsigned i = 0; i != RVLocs.size(); ++i) {
CCValAssign &VA = RVLocs[i];
SDValue Val = OutVals[i];
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
switch (VA.getLocInfo()) {
default:
// Loc info must be one of Full, BCvt, SExt, ZExt, or AExt.
llvm_unreachable("Unknown loc info!");
case CCValAssign::Full:
break;
case CCValAssign::BCvt:
Val = DAG.getBitcast(VA.getLocVT(), Val);
break;
case CCValAssign::SExt:
Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val);
break;
case CCValAssign::ZExt:
Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val);
break;
case CCValAssign::AExt:
Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val);
break;
}
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Val, Flag);
// Guarantee that all emitted copies are stuck together with flags.
Flag = Chain.getValue(1);

54
llvm/test/CodeGen/Hexagon/isel/logical.ll
View File

@ -16,12 +16,6 @@ define i1 @f0(i32 %a0, i32 %a1) #1 {
; CHECK-NEXT: p0 = and(p0,p1)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r2 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: p0 = tstbit(r2,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
@ -49,12 +43,6 @@ define i1 @f1(i32 %a0, i32 %a1) #1 {
; CHECK-NEXT: p0 = or(p0,p1)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r2 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: p0 = tstbit(r2,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
@ -82,12 +70,6 @@ define i1 @f2(i32 %a0, i32 %a1) #1 {
; CHECK-NEXT: p0 = xor(p0,p1)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r2 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: p0 = tstbit(r2,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
@ -127,7 +109,7 @@ define i1 @f3(i32 %a0, i32 %a1) #1 {
; CHECK-NEXT: p0 = and(p0,!p1)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: r0 = mux(p0,#1,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31
@ -167,7 +149,7 @@ define i1 @f4(i32 %a0, i32 %a1) #1 {
; CHECK-NEXT: p0 = or(p0,!p1)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: r0 = mux(p0,#1,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31
@ -198,12 +180,6 @@ define i1 @f5(i32 %a0, i32 %a1, i32 %a2) #1 {
; CHECK-NEXT: p0 = and(p2,and(p0,p1))
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r2 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: p0 = tstbit(r2,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
@ -237,12 +213,6 @@ define i1 @f6(i32 %a0, i32 %a1, i32 %a2) #1 {
; CHECK-NEXT: p0 = and(p2,or(p0,p1))
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r2 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: p0 = tstbit(r2,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
@ -276,12 +246,6 @@ define i1 @f7(i32 %a0, i32 %a1, i32 %a2) #1 {
; CHECK-NEXT: p0 = or(p2,and(p0,p1))
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r2 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: p0 = tstbit(r2,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
@ -315,12 +279,6 @@ define i1 @f8(i32 %a0, i32 %a1, i32 %a2) #1 {
; CHECK-NEXT: p0 = or(p2,or(p0,p1))
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r2 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: p0 = tstbit(r2,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: }
; CHECK-NEXT: {
@ -372,7 +330,7 @@ define i1 @f9(i32 %a0, i32 %a1, i32 %a2) #1 {
; CHECK-NEXT: p0 = and(p2,and(p0,!p1))
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: r0 = mux(p0,#1,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31
@ -424,7 +382,7 @@ define i1 @f10(i32 %a0, i32 %a1, i32 %a2) #1 {
; CHECK-NEXT: p0 = and(p2,or(p0,!p1))
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: r0 = mux(p0,#1,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31
@ -476,7 +434,7 @@ define i1 @f11(i32 %a0, i32 %a1, i32 %a2) #1 {
; CHECK-NEXT: p0 = or(p2,and(p0,!p1))
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: r0 = mux(p0,#1,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31
@ -528,7 +486,7 @@ define i1 @f12(i32 %a0, i32 %a1, i32 %a2) #1 {
; CHECK-NEXT: p0 = or(p2,or(p0,!p1))
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = p0
; CHECK-NEXT: r0 = mux(p0,#1,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: jumpr r31

21
llvm/test/CodeGen/Hexagon/predicate-copy.ll
View File

@ -1,10 +1,19 @@
; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon < %s | FileCheck %s
; CHECK: r{{[0-9]+}} = p{{[0-9]+}}
define i1 @f0() #0 {
define i1 @f0(i32 %a0) #0 {
; CHECK-LABEL: f0:
; CHECK: // %bb.0: // %b0
; CHECK-NEXT: {
; CHECK-NEXT: p0 = cmp.eq(r0,#0)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = mux(p0,#0,#1)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
b0:
ret i1 false
%v0 = icmp ne i32 %a0, 0
ret i1 %v0
}
attributes #0 = { nounwind "target-cpu"="hexagonv5" }
attributes #0 = { nounwind "target-cpu"="hexagonv66" }

9
llvm/test/MC/Hexagon/inst_cmp_eq.ll
View File

@ -1,12 +1,11 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -d - | FileCheck %s
define i1 @foo (i32 %a, i32 %b)
{
%1 = icmp eq i32 %a, %b
ret i1 %1
define i1 @f0(i32 %a0, i32 %a1) {
%v0 = icmp eq i32 %a0, %a1
ret i1 %v0
}
; CHECK: p0 = cmp.eq(r0,r1)
; CHECK: r0 = p0
; CHECK: r0 = mux(p0,#1,#0)
; CHECK: jumpr r31

9
llvm/test/MC/Hexagon/inst_cmp_eqi.ll
View File

@ -1,12 +1,11 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -d - | FileCheck %s
define i1 @foo (i32 %a)
{
%1 = icmp eq i32 %a, 42
ret i1 %1
define i1 @f0(i32 %a0) {
%v0 = icmp eq i32 %a0, 42
ret i1 %v0
}
; CHECK: p0 = cmp.eq(r0,#42)
; CHECK: r0 = p0
; CHECK: r0 = mux(p0,#1,#0)
; CHECK: jumpr r31

11
llvm/test/MC/Hexagon/inst_cmp_gt.ll
View File

@ -1,12 +1,11 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -d - | FileCheck %s
define i1 @foo (i32 %a, i32 %b)
{
%1 = icmp sgt i32 %a, %b
ret i1 %1
define i1 @f0(i32 %a0, i32 %a1) {
%v0 = icmp sgt i32 %a0, %a1
ret i1 %v0
}
; CHECK: p0 = cmp.gt(r0,r1)
; CHECK: r0 = p0
; CHECK: jumpr r31 }
; CHECK: r0 = mux(p0,#1,#0)
; CHECK: jumpr r31

9
llvm/test/MC/Hexagon/inst_cmp_gti.ll
View File

@ -1,12 +1,11 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -d - | FileCheck %s
define i1 @foo (i32 %a)
{
%1 = icmp sgt i32 %a, 42
ret i1 %1
define i1 @f0(i32 %a0) {
%v0 = icmp sgt i32 %a0, 42
ret i1 %v0
}
; CHECK: p0 = cmp.gt(r0,#42)
; CHECK: r0 = p0
; CHECK: r0 = mux(p0,#1,#0)
; CHECK: jumpr r31

9
llvm/test/MC/Hexagon/inst_cmp_lt.ll
View File

@ -1,12 +1,11 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -d - | FileCheck %s
define i1 @foo (i32 %a, i32 %b)
{
%1 = icmp slt i32 %a, %b
ret i1 %1
define i1 @f0(i32 %a0, i32 %a1) {
%v0 = icmp slt i32 %a0, %a1
ret i1 %v0
}
; CHECK: p0 = cmp.gt(r1,r0)
; CHECK: r0 = p0
; CHECK: r0 = mux(p0,#1,#0)
; CHECK: jumpr r31

9
llvm/test/MC/Hexagon/inst_cmp_ugt.ll
View File

@ -1,12 +1,11 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -d - | FileCheck %s
define i1 @foo (i32 %a, i32 %b)
{
%1 = icmp ugt i32 %a, %b
ret i1 %1
define i1 @f0(i32 %a0, i32 %a1) {
%v0 = icmp ugt i32 %a0, %a1
ret i1 %v0
}
; CHECK: p0 = cmp.gtu(r0,r1)
; CHECK: r0 = p0
; CHECK: r0 = mux(p0,#1,#0)
; CHECK: jumpr r31

9
llvm/test/MC/Hexagon/inst_cmp_ugti.ll
View File

@ -1,12 +1,11 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -d - | FileCheck %s
define i1 @foo (i32 %a)
{
%1 = icmp ugt i32 %a, 42
ret i1 %1
define i1 @f0(i32 %a0) {
%v0 = icmp ugt i32 %a0, 42
ret i1 %v0
}
; CHECK: p0 = cmp.gtu(r0,#42)
; CHECK: r0 = p0
; CHECK: r0 = mux(p0,#1,#0)
; CHECK: jumpr r31

9
llvm/test/MC/Hexagon/inst_cmp_ult.ll
View File

@ -1,12 +1,11 @@
;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -d - | FileCheck %s
define i1 @foo (i32 %a, i32 %b)
{
%1 = icmp ult i32 %a, %b
ret i1 %1
define i1 @f0(i32 %a0, i32 %a1) {
%v0 = icmp ult i32 %a0, %a1
ret i1 %v0
}
; CHECK: p0 = cmp.gtu(r1,r0)
; CHECK: r0 = p0
; CHECK: r0 = mux(p0,#1,#0)
; CHECK: jumpr r31