From 06225084b9ae5fb01343c476723654f0864ada64 Mon Sep 17 00:00:00 2001 From: "Vikram S. Adve" Date: Tue, 18 Sep 2001 12:41:43 +0000 Subject: [PATCH] Minor fixes: renamed target machine files; fold sched info into TargetMachine. llvm-svn: 603 --- llvm/include/llvm/CodeGen/InstrForest.h | 50 +++++++++++---------- llvm/include/llvm/CodeGen/InstrScheduling.h | 4 +- llvm/include/llvm/CodeGen/MachineInstr.h | 3 +- llvm/include/llvm/CodeGen/RegClass.h | 4 +- llvm/lib/CodeGen/RegAlloc/RegClass.h | 4 +- 5 files changed, 33 insertions(+), 32 deletions(-) diff --git a/llvm/include/llvm/CodeGen/InstrForest.h b/llvm/include/llvm/CodeGen/InstrForest.h index 47a12ace6b7e..6fe622d9fc3f 100644 --- a/llvm/include/llvm/CodeGen/InstrForest.h +++ b/llvm/include/llvm/CodeGen/InstrForest.h @@ -1,25 +1,25 @@ -/* $Id$ -*-c++-*- - **************************************************************************** - * File: - * InstrForest.h - * - * Purpose: - * Convert SSA graph to instruction trees for instruction selection. - * - * Strategy: - * The basic idea is that we would like to group instructions into a single - * tree if one or more of them might be potentially combined into a single - * complex instruction in the target machine. - * Since this grouping is completely machine-independent, it is as - * aggressive as possible. In particular, we group two instructions - * O and I if: - * (1) Instruction O computes an operand of instruction I, and - * (2) O and I are part of the same basic block, and - * (3) O has only a single use, viz., I. - * - * History: - * 6/28/01 - Vikram Adve - Created - ***************************************************************************/ +// $Id$ -*-c++-*- +//*************************************************************************** +// File: +// InstrForest.h +// +// Purpose: +// Convert SSA graph to instruction trees for instruction selection. +// +// Strategy: +// The basic idea is that we would like to group instructions into a single +// tree if one or more of them might be potentially combined into a single +// complex instruction in the target machine. +// Since this grouping is completely machine-independent, it is as +// aggressive as possible. In particular, we group two instructions +// O and I if: +// (1) Instruction O computes an operand of instruction I, and +// (2) O and I are part of the same basic block, and +// (3) O has only a single use, viz., I. +// +// History: +// 6/28/01 - Vikram Adve - Created +//**************************************************************************/ #ifndef LLVM_CODEGEN_INSTRFOREST_H #define LLVM_CODEGEN_INSTRFOREST_H @@ -235,11 +235,13 @@ protected: //------------------------------------------------------------------------ class InstrForest : private hash_map { +private: hash_set treeRoots; public: - InstrForest(Method *M); - + /*ctor*/ InstrForest (Method *M); + /*dtor*/ ~InstrForest (); + inline InstructionNode *getTreeNodeForInstr(Instruction* instr) { return (*this)[instr]; } diff --git a/llvm/include/llvm/CodeGen/InstrScheduling.h b/llvm/include/llvm/CodeGen/InstrScheduling.h index cfaa8b05ef42..8f88a61590a1 100644 --- a/llvm/include/llvm/CodeGen/InstrScheduling.h +++ b/llvm/include/llvm/CodeGen/InstrScheduling.h @@ -42,8 +42,8 @@ extern cl::Enum SchedDebugLevel; // are still in SSA form. //--------------------------------------------------------------------------- -bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &Target, - const MachineSchedInfo &schedInfo); +bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &Target); + //--------------------------------------------------------------------------- // Function: ScheduleInstructions diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 339371227d2f..66e91b28e42c 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -19,7 +19,7 @@ #include "llvm/CodeGen/InstrForest.h" #include "llvm/Support/DataTypes.h" #include "llvm/Support/NonCopyable.h" -#include "llvm/Target/InstInfo.h" +#include "llvm/Target/MachineInstrInfo.h" template class ValOpIterator; @@ -86,7 +86,6 @@ private: unsigned int regNum; // register number for an explicit register // will be set for a value after reg allocation bool isDef; // is this a defition for the value - // made public for faster access public: /*ctor*/ MachineOperand (); diff --git a/llvm/include/llvm/CodeGen/RegClass.h b/llvm/include/llvm/CodeGen/RegClass.h index 723443da9ad6..d08ed3a6594c 100644 --- a/llvm/include/llvm/CodeGen/RegClass.h +++ b/llvm/include/llvm/CodeGen/RegClass.h @@ -21,8 +21,8 @@ #include "llvm/CodeGen/IGNode.h" #include "llvm/CodeGen/InterferenceGraph.h" -#include "llvm/Target/Machine.h" -#include "llvm/Target/RegInfo.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/MachineRegInfo.h" #include typedef vector ReservedColorListType; diff --git a/llvm/lib/CodeGen/RegAlloc/RegClass.h b/llvm/lib/CodeGen/RegAlloc/RegClass.h index 723443da9ad6..d08ed3a6594c 100644 --- a/llvm/lib/CodeGen/RegAlloc/RegClass.h +++ b/llvm/lib/CodeGen/RegAlloc/RegClass.h @@ -21,8 +21,8 @@ #include "llvm/CodeGen/IGNode.h" #include "llvm/CodeGen/InterferenceGraph.h" -#include "llvm/Target/Machine.h" -#include "llvm/Target/RegInfo.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/Target/MachineRegInfo.h" #include typedef vector ReservedColorListType;