forked from OSchip/llvm-project
Minor fixes: renamed target machine files; fold sched info into TargetMachine.
llvm-svn: 603
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@ -1,25 +1,25 @@
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/* $Id$ -*-c++-*-
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****************************************************************************
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* File:
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* InstrForest.h
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*
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* Purpose:
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* Convert SSA graph to instruction trees for instruction selection.
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*
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* Strategy:
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* The basic idea is that we would like to group instructions into a single
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* tree if one or more of them might be potentially combined into a single
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* complex instruction in the target machine.
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* Since this grouping is completely machine-independent, it is as
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* aggressive as possible. In particular, we group two instructions
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* O and I if:
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* (1) Instruction O computes an operand of instruction I, and
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* (2) O and I are part of the same basic block, and
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* (3) O has only a single use, viz., I.
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*
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* History:
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* 6/28/01 - Vikram Adve - Created
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***************************************************************************/
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// $Id$ -*-c++-*-
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//***************************************************************************
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// File:
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// InstrForest.h
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//
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// Purpose:
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// Convert SSA graph to instruction trees for instruction selection.
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//
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// Strategy:
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// The basic idea is that we would like to group instructions into a single
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// tree if one or more of them might be potentially combined into a single
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// complex instruction in the target machine.
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// Since this grouping is completely machine-independent, it is as
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// aggressive as possible. In particular, we group two instructions
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// O and I if:
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// (1) Instruction O computes an operand of instruction I, and
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// (2) O and I are part of the same basic block, and
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// (3) O has only a single use, viz., I.
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//
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// History:
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// 6/28/01 - Vikram Adve - Created
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//**************************************************************************/
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#ifndef LLVM_CODEGEN_INSTRFOREST_H
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#define LLVM_CODEGEN_INSTRFOREST_H
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@ -235,11 +235,13 @@ protected:
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//------------------------------------------------------------------------
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class InstrForest : private hash_map<const Instruction*, InstructionNode*> {
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private:
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hash_set<InstructionNode*> treeRoots;
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public:
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InstrForest(Method *M);
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/*ctor*/ InstrForest (Method *M);
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/*dtor*/ ~InstrForest ();
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inline InstructionNode *getTreeNodeForInstr(Instruction* instr) {
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return (*this)[instr];
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}
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@ -42,8 +42,8 @@ extern cl::Enum<SchedDebugLevel_t> SchedDebugLevel;
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// are still in SSA form.
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//---------------------------------------------------------------------------
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bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &Target,
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const MachineSchedInfo &schedInfo);
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bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &Target);
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//---------------------------------------------------------------------------
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// Function: ScheduleInstructions
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@ -19,7 +19,7 @@
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#include "llvm/CodeGen/InstrForest.h"
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#include "llvm/Support/DataTypes.h"
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#include "llvm/Support/NonCopyable.h"
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#include "llvm/Target/InstInfo.h"
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#include "llvm/Target/MachineInstrInfo.h"
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template<class _MI, class _V> class ValOpIterator;
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@ -86,7 +86,6 @@ private:
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unsigned int regNum; // register number for an explicit register
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// will be set for a value after reg allocation
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bool isDef; // is this a defition for the value
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// made public for faster access
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public:
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/*ctor*/ MachineOperand ();
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@ -21,8 +21,8 @@
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#include "llvm/CodeGen/IGNode.h"
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#include "llvm/CodeGen/InterferenceGraph.h"
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#include "llvm/Target/Machine.h"
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#include "llvm/Target/RegInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include <stack>
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typedef vector<unsigned int> ReservedColorListType;
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@ -21,8 +21,8 @@
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#include "llvm/CodeGen/IGNode.h"
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#include "llvm/CodeGen/InterferenceGraph.h"
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#include "llvm/Target/Machine.h"
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#include "llvm/Target/RegInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/MachineRegInfo.h"
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#include <stack>
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typedef vector<unsigned int> ReservedColorListType;
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