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[ValueTracking] Out of range shifts might be undef
If it is possible for the RHS of a shift operation to be greater than or equal to the bit-width, then the result might be undef, and we can't report any known bits. In some cases, this was allowing a transformation in instcombine which widened an undef value from i1 to i32, increasing the range of values that a function could return. Differential revision: https://reviews.llvm.org/D30781 llvm-svn: 297724
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@ -848,6 +848,14 @@ static void computeKnownBitsFromShiftOperator(
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computeKnownBits(I->getOperand(1), KnownZero, KnownOne, Depth + 1, Q);
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// If the shift amount could be greater than or equal to the bit-width of the LHS, the
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// value could be undef, so we don't know anything about it.
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if ((~KnownZero).uge(BitWidth)) {
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KnownZero.clearAllBits();
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KnownOne.clearAllBits();
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return;
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}
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// Note: We cannot use KnownZero.getLimitedValue() here, because if
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// BitWidth > 64 and any upper bits are known, we'll end up returning the
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// limit value (which implies all bits are known).
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@ -19,3 +19,33 @@ define i8 @zext_or_icmp_icmp(i8 %a, i8 %b) {
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; CHECK-NEXT: ret i8 %zext
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}
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; Here, widening the or from i1 to i32 and removing one of the icmps would
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; widen an undef value (created by the out-of-range shift), increasing the
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; range of valid values for the return, so we can't do it.
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define i32 @dont_widen_undef() {
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entry:
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br label %block2
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block1:
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br label %block2
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block2:
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%m.011 = phi i32 [ 33, %entry ], [ 0, %block1 ]
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%cmp.i = icmp ugt i32 %m.011, 1
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%m.1.op = lshr i32 1, %m.011
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%sext.mask = and i32 %m.1.op, 65535
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%cmp115 = icmp ne i32 %sext.mask, 0
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%cmp1 = or i1 %cmp.i, %cmp115
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%conv2 = zext i1 %cmp1 to i32
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ret i32 %conv2
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; CHECK-LABEL: dont_widen_undef(
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; CHECK: %m.011 = phi i32 [ 33, %entry ], [ 0, %block1 ]
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; CHECK-NEXT: %cmp.i = icmp ugt i32 %m.011, 1
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; CHECK-NEXT: %m.1.op = lshr i32 1, %m.011
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; CHECK-NEXT: %sext.mask = and i32 %m.1.op, 65535
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; CHECK-NEXT: %cmp115 = icmp ne i32 %sext.mask, 0
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; CHECK-NEXT: %cmp1 = or i1 %cmp.i, %cmp115
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; CHECK-NEXT: %conv2 = zext i1 %cmp1 to i32
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; CHECK-NEXT: ret i32 %conv2
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}
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