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R600/SI: Fix verifier error with pseudo store instructions. 

Use i32 instead of specifying SReg_32. When this is
the pseudo INDIRECT_BASE_ADDR, this would give a bogus
verifier error.

llvm-svn: 207770
This commit is contained in:
Matt Arsenault 2014-05-01 16:37:52 +00:00
parent ffc1c6af49
commit 06028dd7be
4 changed files with 5 additions and 5 deletions
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2
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -137,7 +137,7 @@ class SGPRImm <dag frag> : PatLeaf<frag, [{
}]>;
def FRAMEri32 : Operand<iPTR> {
let MIOperandInfo = (ops SReg_32:$ptr, i32imm:$index);
let MIOperandInfo = (ops i32:$ptr, i32imm:$index);
}
//===----------------------------------------------------------------------===//

2
llvm/test/CodeGen/R600/array-ptr-calc-i32.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
declare i32 @llvm.SI.tid() nounwind readnone
declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate

2
llvm/test/CodeGen/R600/insert_vector_elt.ll
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@ -1,4 +1,4 @@
; RUN: llc -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck -check-prefix=SI %s
; FIXME: Broken on evergreen
; FIXME: For some reason the 8 and 16 vectors are being stored as

4
llvm/test/CodeGen/R600/private-memory.ll
View File

@ -1,5 +1,5 @@
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK --check-prefix=FUNC
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck %s --check-prefix=R600-CHECK --check-prefix=FUNC
; RUN: llc -verify-machineinstrs -march=r600 -mcpu=SI < %s | FileCheck %s --check-prefix=SI-CHECK --check-prefix=FUNC
; This test checks that uses and defs of the AR register happen in the same
; instruction clause.