forked from OSchip/llvm-project
Make post regalloc machine licm functional. It now passes all of MultiSource.
llvm-svn: 100742
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@ -57,12 +57,11 @@ namespace {
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// Various analyses that we use...
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AliasAnalysis *AA; // Alias analysis info.
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MachineLoopInfo *LI; // Current MachineLoopInfo
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MachineLoopInfo *MLI; // Current MachineLoopInfo
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MachineDominatorTree *DT; // Machine dominator tree for the cur loop
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// State that is updated as we process loops
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bool Changed; // True if a loop is changed.
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bool FirstInLoop; // True if it's the first LICM in the loop.
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MachineLoop *CurLoop; // The current loop we are working on.
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MachineBasicBlock *CurPreheader; // The preheader for CurLoop.
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@ -99,6 +98,35 @@ namespace {
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}
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private:
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/// CandidateInfo - Keep track of information about hoisting candidates.
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struct CandidateInfo {
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MachineInstr *MI;
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int FI;
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unsigned Def;
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CandidateInfo(MachineInstr *mi, int fi, unsigned def)
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: MI(mi), FI(fi), Def(def) {}
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};
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/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
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/// invariants out to the preheader.
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void HoistRegionPostRA(MachineDomTreeNode *N);
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/// HoistPostRA - When an instruction is found to only use loop invariant
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/// operands that is safe to hoist, this instruction is called to do the
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/// dirty work.
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void HoistPostRA(MachineInstr *MI, unsigned Def);
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/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
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/// gather register def and frame object update information.
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void ProcessMI(MachineInstr *MI, unsigned *PhysRegDefs,
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SmallSet<int, 32> &StoredFIs,
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SmallVector<CandidateInfo, 32> &Candidates);
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/// AddToLiveIns - Add 'Reg' to the livein sets of BBs in the backedge path
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/// from MBB to LoopHeader (inclusive).
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void AddToLiveIns(unsigned Reg,
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MachineBasicBlock *MBB, MachineBasicBlock *LoopHeader);
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/// IsLoopInvariantInst - Returns true if the instruction is loop
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/// invariant. I.e., all virtual register operands are defined outside of
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/// the loop, physical registers aren't accessed (explicitly or implicitly),
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@ -117,7 +145,6 @@ namespace {
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/// pass without iteration.
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///
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void HoistRegion(MachineDomTreeNode *N);
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void HoistRegionPostRA(MachineDomTreeNode *N);
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/// isLoadFromConstantMemory - Return true if the given instruction is a
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/// load from constant memory.
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@ -145,7 +172,6 @@ namespace {
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/// that is safe to hoist, this instruction is called to do the dirty work.
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///
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void Hoist(MachineInstr *MI);
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void HoistPostRA(MachineInstr *MI);
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/// InitCSEMap - Initialize the CSE map with instructions that are in the
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/// current loop preheader that may become duplicates of instructions that
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@ -181,7 +207,7 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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else
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DEBUG(dbgs() << "******** Post-regalloc Machine LICM ********\n");
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Changed = FirstInLoop = false;
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Changed = false;
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TM = &MF.getTarget();
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TII = TM->getInstrInfo();
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TRI = TM->getRegisterInfo();
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@ -190,15 +216,16 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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AllocatableSet = TRI->getAllocatableSet(MF);
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// Get our Loop information...
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LI = &getAnalysis<MachineLoopInfo>();
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DT = &getAnalysis<MachineDominatorTree>();
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AA = &getAnalysis<AliasAnalysis>();
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MLI = &getAnalysis<MachineLoopInfo>();
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DT = &getAnalysis<MachineDominatorTree>();
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AA = &getAnalysis<AliasAnalysis>();
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for (MachineLoopInfo::iterator I = LI->begin(), E = LI->end(); I != E; ++I) {
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for (MachineLoopInfo::iterator I = MLI->begin(), E = MLI->end(); I != E; ++I){
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CurLoop = *I;
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// Only visit outer-most preheader-sporting loops.
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if (!LoopIsOuterMostWithPreheader(CurLoop))
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// If this is done before regalloc, only visit outer-most preheader-sporting
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// loops.
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if (PreRegAlloc && !LoopIsOuterMostWithPreheader(CurLoop))
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continue;
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// Determine the block to which to hoist instructions. If we can't find a
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@ -213,7 +240,6 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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// CSEMap is initialized for loop header when the first instruction is
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// being hoisted.
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FirstInLoop = true;
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MachineDomTreeNode *N = DT->getNode(CurLoop->getHeader());
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if (!PreRegAlloc)
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HoistRegionPostRA(N);
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@ -226,6 +252,95 @@ bool MachineLICM::runOnMachineFunction(MachineFunction &MF) {
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return Changed;
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}
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/// InstructionStoresToFI - Return true if instruction stores to the
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/// specified frame.
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static bool InstructionStoresToFI(const MachineInstr *MI, int FI) {
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for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
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oe = MI->memoperands_end(); o != oe; ++o) {
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if (!(*o)->isStore() || !(*o)->getValue())
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continue;
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if (const FixedStackPseudoSourceValue *Value =
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dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
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if (Value->getFrameIndex() == FI)
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return true;
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}
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}
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return false;
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}
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/// ProcessMI - Examine the instruction for potentai LICM candidate. Also
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/// gather register def and frame object update information.
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void MachineLICM::ProcessMI(MachineInstr *MI,
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unsigned *PhysRegDefs,
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SmallSet<int, 32> &StoredFIs,
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SmallVector<CandidateInfo, 32> &Candidates) {
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bool RuledOut = false;
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unsigned Def = 0;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (MO.isFI()) {
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// Remember if the instruction stores to the frame index.
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int FI = MO.getIndex();
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if (!StoredFIs.count(FI) &&
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MFI->isSpillSlotObjectIndex(FI) &&
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InstructionStoresToFI(MI, FI))
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StoredFIs.insert(FI);
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continue;
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}
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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"Not expecting virtual register!");
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if (!MO.isDef())
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continue;
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if (MO.isImplicit()) {
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++PhysRegDefs[Reg];
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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++PhysRegDefs[*AS];
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if (!MO.isDead())
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// Non-dead implicit def? This cannot be hoisted.
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RuledOut = true;
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// No need to check if a dead implicit def is also defined by
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// another instruction.
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continue;
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}
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// FIXME: For now, avoid instructions with multiple defs, unless
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// it's a dead implicit def.
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if (Def)
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RuledOut = true;
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else
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Def = Reg;
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// If we have already seen another instruction that defines the same
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// register, then this is not safe.
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if (++PhysRegDefs[Reg] > 1)
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// MI defined register is seen defined by another instruction in
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// the loop, it cannot be a LICM candidate.
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RuledOut = true;
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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if (++PhysRegDefs[*AS] > 1)
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RuledOut = true;
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}
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// FIXME: Only consider reloads for now. We should be able to handle
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// remats which does not have register operands.
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if (Def && !RuledOut) {
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int FI;
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if (TII->isLoadFromStackSlot(MI, FI) &&
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MFI->isSpillSlotObjectIndex(FI))
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Candidates.push_back(CandidateInfo(MI, FI, Def));
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}
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}
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/// HoistRegionPostRA - Walk the specified region of the CFG and hoist loop
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/// invariants out to the preheader.
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void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) {
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assert(N != 0 && "Null dominator tree node?");
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@ -233,7 +348,7 @@ void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) {
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unsigned *PhysRegDefs = new unsigned[NumRegs];
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std::fill(PhysRegDefs, PhysRegDefs + NumRegs, 0);
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SmallVector<std::pair<MachineInstr*, int>, 32> Candidates;
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SmallVector<CandidateInfo, 32> Candidates;
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SmallSet<int, 32> StoredFIs;
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// Walk the entire region, count number of defs for each register, and
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@ -244,62 +359,23 @@ void MachineLICM::HoistRegionPostRA(MachineDomTreeNode *N) {
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N = WorkList.pop_back_val();
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MachineBasicBlock *BB = N->getBlock();
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if (!CurLoop->contains(BB))
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if (!CurLoop->contains(MLI->getLoopFor(BB)))
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continue;
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// Conservatively treat live-in's as an external def.
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// FIXME: That means a reload that's reused into a fallthrough block
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// will not be LICM'ed.
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// FIXME: That means a reload that're reused in successor block(s) will not
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// be LICM'ed.
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for (MachineBasicBlock::const_livein_iterator I = BB->livein_begin(),
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E = BB->livein_end(); I != E; ++I) {
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unsigned Reg = *I;
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++PhysRegDefs[Reg];
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for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
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++PhysRegDefs[*SR];
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for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS)
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++PhysRegDefs[*AS];
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}
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for (MachineBasicBlock::iterator
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MII = BB->begin(), E = BB->end(); MII != E; ++MII) {
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bool RuledOut = false;
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bool SeenDef = false;
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MachineInstr *MI = &*MII;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
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"Not expecting virtual register!");
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if (MO.isDef()) {
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SeenDef = true;
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if (++PhysRegDefs[Reg] > 1)
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// MI defined register is seen defined by another instruction in
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// the loop, it cannot be a LICM candidate.
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RuledOut = true;
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for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR)
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if (++PhysRegDefs[*SR] > 1)
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RuledOut = true;
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}
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}
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// FIXME: Only consider reloads for now. We should be able to handle
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// remat which does not have register operands.
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bool SkipCheck = false;
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int FI;
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if (SeenDef && !RuledOut) {
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if (TII->isLoadFromStackSlot(MI, FI) &&
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MFI->isSpillSlotObjectIndex(FI)) {
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Candidates.push_back(std::make_pair(MI, FI));
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SkipCheck = true;
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}
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}
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// If MI is a store to a stack slot, remember the slot. An instruction
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// loads from this slot cannot be a LICM candidate.
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if (!SkipCheck && TII->isStoreToStackSlot(MI, FI))
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StoredFIs.insert(FI);
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ProcessMI(MI, PhysRegDefs, StoredFIs, Candidates);
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}
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const std::vector<MachineDomTreeNode*> &Children = N->getChildren();
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// 2. If the candidate is a load from stack slot (always true for now),
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// check if the slot is stored anywhere in the loop.
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for (unsigned i = 0, e = Candidates.size(); i != e; ++i) {
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bool Safe = true;
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int FI = Candidates[i].second;
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if (StoredFIs.count(FI))
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if (StoredFIs.count(Candidates[i].FI))
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continue;
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MachineInstr *MI = Candidates[i].first;
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for (unsigned j = 0, ee = MI->getNumOperands(); j != ee; ++j) {
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const MachineOperand &MO = MI->getOperand(j);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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if (MO.isDef() && PhysRegDefs[Reg] > 1) {
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Safe = false;
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break;
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}
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}
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if (Safe)
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HoistPostRA(MI);
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if (PhysRegDefs[Candidates[i].Def] == 1)
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HoistPostRA(Candidates[i].MI, Candidates[i].Def);
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}
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}
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void MachineLICM::HoistPostRA(MachineInstr *MI) {
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/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
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/// backedge path from MBB to LoopHeader.
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void MachineLICM::AddToLiveIns(unsigned Reg, MachineBasicBlock *MBB,
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MachineBasicBlock *LoopHeader) {
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SmallPtrSet<MachineBasicBlock*, 4> Visited;
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SmallVector<MachineBasicBlock*, 4> WorkList;
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WorkList.push_back(MBB);
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do {
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MBB = WorkList.pop_back_val();
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if (!Visited.insert(MBB))
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continue;
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MBB->addLiveIn(Reg);
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if (MBB == LoopHeader)
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continue;
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for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
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E = MBB->pred_end(); PI != E; ++PI)
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WorkList.push_back(*PI);
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} while (!WorkList.empty());
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}
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/// HoistPostRA - When an instruction is found to only use loop invariant
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/// operands that is safe to hoist, this instruction is called to do the
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/// dirty work.
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void MachineLICM::HoistPostRA(MachineInstr *MI, unsigned Def) {
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// Now move the instructions to the predecessor, inserting it before any
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// terminator instructions.
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DEBUG({
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});
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// Splice the instruction to the preheader.
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CurPreheader->splice(CurPreheader->getFirstTerminator(),MI->getParent(),MI);
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MachineBasicBlock *MBB = MI->getParent();
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CurPreheader->splice(CurPreheader->getFirstTerminator(), MBB, MI);
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// Add register to livein list to BBs in the path from loop header to original
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// BB. Note, currently it's not necessary to worry about adding it to all BB's
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// with uses. Reload that're reused in successor block(s) are not being
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// hoisted.
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AddToLiveIns(Def, MBB, CurLoop->getHeader());
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++NumPostRAHoisted;
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Changed = true;
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