forked from OSchip/llvm-project
[RISCV] Basic jump table lowering
This patch enables jump table lowering in the RISC-V backend. In addition to the test case included, the new lowering was tested by compiling the OCaml runtime and running it under qemu. Differential Revision: https://reviews.llvm.org/D92097
This commit is contained in:
Nandor Licker
parent
28b00ba731
commit
0586f048d7
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@ -305,6 +305,9 @@ public:
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case MachineOperand::MO_BlockAddress:
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return addBlockAddress(Disp.getBlockAddress(), Disp.getOffset() + off,
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TargetFlags);
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case MachineOperand::MO_JumpTableIndex:
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assert(off == 0 && "cannot create offset into jump tables");
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return addJumpTableIndex(Disp.getIndex(), TargetFlags);
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}
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}
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@ -323,6 +323,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
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setOperationAction(ISD::BlockAddress, XLenVT, Custom);
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setOperationAction(ISD::ConstantPool, XLenVT, Custom);
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setOperationAction(ISD::JumpTable, XLenVT, Custom);
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setOperationAction(ISD::GlobalTLSAddress, XLenVT, Custom);
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@ -367,8 +368,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setMinFunctionAlignment(FunctionAlignment);
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setPrefFunctionAlignment(FunctionAlignment);
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// Effectively disable jump table generation.
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setMinimumJumpTableEntries(INT_MAX);
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setMinimumJumpTableEntries(5);
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// Jumps are expensive, compared to logic
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setJumpIsExpensive();
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@ -565,6 +565,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
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return lowerBlockAddress(Op, DAG);
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case ISD::ConstantPool:
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return lowerConstantPool(Op, DAG);
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case ISD::JumpTable:
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return lowerJumpTable(Op, DAG);
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case ISD::GlobalTLSAddress:
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return lowerGlobalTLSAddress(Op, DAG);
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case ISD::SELECT:
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@ -643,6 +645,11 @@ static SDValue getTargetNode(ConstantPoolSDNode *N, SDLoc DL, EVT Ty,
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N->getOffset(), Flags);
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}
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static SDValue getTargetNode(JumpTableSDNode *N, SDLoc DL, EVT Ty,
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SelectionDAG &DAG, unsigned Flags) {
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return DAG.getTargetJumpTable(N->getIndex(), Ty, Flags);
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}
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template <class NodeTy>
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SDValue RISCVTargetLowering::getAddr(NodeTy *N, SelectionDAG &DAG,
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bool IsLocal) const {
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@ -720,6 +727,13 @@ SDValue RISCVTargetLowering::lowerConstantPool(SDValue Op,
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return getAddr(N, DAG);
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}
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SDValue RISCVTargetLowering::lowerJumpTable(SDValue Op,
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SelectionDAG &DAG) const {
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JumpTableSDNode *N = cast<JumpTableSDNode>(Op);
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return getAddr(N, DAG);
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}
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SDValue RISCVTargetLowering::getStaticTLSAddr(GlobalAddressSDNode *N,
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SelectionDAG &DAG,
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bool UseGOT) const {
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@ -257,6 +257,7 @@ private:
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SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerSELECT(SDValue Op, SelectionDAG &DAG) const;
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SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
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@ -122,6 +122,9 @@ bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
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break;
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}
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return true;
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}
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@ -1,39 +1,145 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; RUN: llc -mtriple=riscv32 -code-model=small -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I-SMALL
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; RUN: llc -mtriple=riscv32 -code-model=medium -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I-MEDIUM
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; RUN: llc -mtriple=riscv64 -code-model=small -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I-SMALL
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; RUN: llc -mtriple=riscv64 -code-model=medium -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV64I-MEDIUM
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define void @jt(i32 %in, i32* %out) nounwind {
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; RV32I-LABEL: jt:
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; RV32I: # %bb.0: # %entry
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; RV32I-NEXT: addi a2, zero, 2
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; RV32I-NEXT: blt a2, a0, .LBB0_4
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; RV32I-NEXT: # %bb.1: # %entry
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; RV32I-NEXT: addi a2, zero, 1
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; RV32I-NEXT: beq a0, a2, .LBB0_7
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; RV32I-NEXT: # %bb.2: # %entry
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; RV32I-NEXT: addi a2, zero, 2
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; RV32I-NEXT: bne a0, a2, .LBB0_10
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; RV32I-NEXT: # %bb.3: # %bb2
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; RV32I-NEXT: addi a0, zero, 3
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; RV32I-NEXT: j .LBB0_9
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; RV32I-NEXT: .LBB0_4: # %entry
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; RV32I-NEXT: addi a2, zero, 3
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; RV32I-NEXT: beq a0, a2, .LBB0_8
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; RV32I-NEXT: # %bb.5: # %entry
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; RV32I-NEXT: addi a2, zero, 4
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; RV32I-NEXT: bne a0, a2, .LBB0_10
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; RV32I-NEXT: # %bb.6: # %bb4
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; RV32I-NEXT: addi a0, zero, 1
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; RV32I-NEXT: j .LBB0_9
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; RV32I-NEXT: .LBB0_7: # %bb1
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; RV32I-NEXT: addi a0, zero, 4
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; RV32I-NEXT: j .LBB0_9
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; RV32I-NEXT: .LBB0_8: # %bb3
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; RV32I-NEXT: addi a0, zero, 2
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; RV32I-NEXT: .LBB0_9: # %exit
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; RV32I-NEXT: sw a0, 0(a1)
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; RV32I-NEXT: .LBB0_10: # %exit
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; RV32I-NEXT: ret
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define void @below_threshold(i32 %in, i32* %out) nounwind {
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; RV32I-SMALL-LABEL: below_threshold:
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; RV32I-SMALL: # %bb.0: # %entry
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; RV32I-SMALL-NEXT: addi a2, zero, 2
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; RV32I-SMALL-NEXT: blt a2, a0, .LBB0_4
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; RV32I-SMALL-NEXT: # %bb.1: # %entry
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; RV32I-SMALL-NEXT: addi a2, zero, 1
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; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_7
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; RV32I-SMALL-NEXT: # %bb.2: # %entry
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; RV32I-SMALL-NEXT: addi a2, zero, 2
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; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
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; RV32I-SMALL-NEXT: # %bb.3: # %bb2
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; RV32I-SMALL-NEXT: addi a0, zero, 3
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; RV32I-SMALL-NEXT: j .LBB0_9
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; RV32I-SMALL-NEXT: .LBB0_4: # %entry
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; RV32I-SMALL-NEXT: addi a2, zero, 3
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; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_8
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; RV32I-SMALL-NEXT: # %bb.5: # %entry
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; RV32I-SMALL-NEXT: addi a2, zero, 4
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; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
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; RV32I-SMALL-NEXT: # %bb.6: # %bb4
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; RV32I-SMALL-NEXT: addi a0, zero, 1
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; RV32I-SMALL-NEXT: j .LBB0_9
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; RV32I-SMALL-NEXT: .LBB0_7: # %bb1
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; RV32I-SMALL-NEXT: addi a0, zero, 4
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; RV32I-SMALL-NEXT: j .LBB0_9
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; RV32I-SMALL-NEXT: .LBB0_8: # %bb3
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; RV32I-SMALL-NEXT: addi a0, zero, 2
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; RV32I-SMALL-NEXT: .LBB0_9: # %exit
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; RV32I-SMALL-NEXT: sw a0, 0(a1)
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; RV32I-SMALL-NEXT: .LBB0_10: # %exit
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; RV32I-SMALL-NEXT: ret
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;
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; RV32I-MEDIUM-LABEL: below_threshold:
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; RV32I-MEDIUM: # %bb.0: # %entry
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; RV32I-MEDIUM-NEXT: addi a2, zero, 2
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; RV32I-MEDIUM-NEXT: blt a2, a0, .LBB0_4
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; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
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; RV32I-MEDIUM-NEXT: addi a2, zero, 1
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; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
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; RV32I-MEDIUM-NEXT: # %bb.2: # %entry
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; RV32I-MEDIUM-NEXT: addi a2, zero, 2
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; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
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; RV32I-MEDIUM-NEXT: # %bb.3: # %bb2
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; RV32I-MEDIUM-NEXT: addi a0, zero, 3
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; RV32I-MEDIUM-NEXT: j .LBB0_9
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; RV32I-MEDIUM-NEXT: .LBB0_4: # %entry
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; RV32I-MEDIUM-NEXT: addi a2, zero, 3
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; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
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; RV32I-MEDIUM-NEXT: # %bb.5: # %entry
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; RV32I-MEDIUM-NEXT: addi a2, zero, 4
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; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
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; RV32I-MEDIUM-NEXT: # %bb.6: # %bb4
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; RV32I-MEDIUM-NEXT: addi a0, zero, 1
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; RV32I-MEDIUM-NEXT: j .LBB0_9
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; RV32I-MEDIUM-NEXT: .LBB0_7: # %bb1
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; RV32I-MEDIUM-NEXT: addi a0, zero, 4
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; RV32I-MEDIUM-NEXT: j .LBB0_9
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; RV32I-MEDIUM-NEXT: .LBB0_8: # %bb3
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; RV32I-MEDIUM-NEXT: addi a0, zero, 2
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; RV32I-MEDIUM-NEXT: .LBB0_9: # %exit
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; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
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; RV32I-MEDIUM-NEXT: .LBB0_10: # %exit
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; RV32I-MEDIUM-NEXT: ret
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;
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; RV64I-SMALL-LABEL: below_threshold:
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; RV64I-SMALL: # %bb.0: # %entry
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; RV64I-SMALL-NEXT: slli a0, a0, 32
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; RV64I-SMALL-NEXT: srli a0, a0, 32
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; RV64I-SMALL-NEXT: addi a2, zero, 2
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; RV64I-SMALL-NEXT: blt a2, a0, .LBB0_4
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; RV64I-SMALL-NEXT: # %bb.1: # %entry
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; RV64I-SMALL-NEXT: addi a2, zero, 1
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; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_7
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; RV64I-SMALL-NEXT: # %bb.2: # %entry
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; RV64I-SMALL-NEXT: addi a2, zero, 2
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; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
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; RV64I-SMALL-NEXT: # %bb.3: # %bb2
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; RV64I-SMALL-NEXT: addi a0, zero, 3
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; RV64I-SMALL-NEXT: j .LBB0_9
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; RV64I-SMALL-NEXT: .LBB0_4: # %entry
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; RV64I-SMALL-NEXT: addi a2, zero, 3
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; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_8
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; RV64I-SMALL-NEXT: # %bb.5: # %entry
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; RV64I-SMALL-NEXT: addi a2, zero, 4
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; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
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; RV64I-SMALL-NEXT: # %bb.6: # %bb4
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; RV64I-SMALL-NEXT: addi a0, zero, 1
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; RV64I-SMALL-NEXT: j .LBB0_9
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; RV64I-SMALL-NEXT: .LBB0_7: # %bb1
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; RV64I-SMALL-NEXT: addi a0, zero, 4
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; RV64I-SMALL-NEXT: j .LBB0_9
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; RV64I-SMALL-NEXT: .LBB0_8: # %bb3
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; RV64I-SMALL-NEXT: addi a0, zero, 2
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; RV64I-SMALL-NEXT: .LBB0_9: # %exit
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; RV64I-SMALL-NEXT: sw a0, 0(a1)
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; RV64I-SMALL-NEXT: .LBB0_10: # %exit
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; RV64I-SMALL-NEXT: ret
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;
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; RV64I-MEDIUM-LABEL: below_threshold:
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; RV64I-MEDIUM: # %bb.0: # %entry
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; RV64I-MEDIUM-NEXT: slli a0, a0, 32
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; RV64I-MEDIUM-NEXT: srli a0, a0, 32
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; RV64I-MEDIUM-NEXT: addi a2, zero, 2
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; RV64I-MEDIUM-NEXT: blt a2, a0, .LBB0_4
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; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
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; RV64I-MEDIUM-NEXT: addi a2, zero, 1
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; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
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; RV64I-MEDIUM-NEXT: # %bb.2: # %entry
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; RV64I-MEDIUM-NEXT: addi a2, zero, 2
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; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
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; RV64I-MEDIUM-NEXT: # %bb.3: # %bb2
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; RV64I-MEDIUM-NEXT: addi a0, zero, 3
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; RV64I-MEDIUM-NEXT: j .LBB0_9
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; RV64I-MEDIUM-NEXT: .LBB0_4: # %entry
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; RV64I-MEDIUM-NEXT: addi a2, zero, 3
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; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
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; RV64I-MEDIUM-NEXT: # %bb.5: # %entry
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; RV64I-MEDIUM-NEXT: addi a2, zero, 4
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; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
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; RV64I-MEDIUM-NEXT: # %bb.6: # %bb4
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; RV64I-MEDIUM-NEXT: addi a0, zero, 1
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; RV64I-MEDIUM-NEXT: j .LBB0_9
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; RV64I-MEDIUM-NEXT: .LBB0_7: # %bb1
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; RV64I-MEDIUM-NEXT: addi a0, zero, 4
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; RV64I-MEDIUM-NEXT: j .LBB0_9
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; RV64I-MEDIUM-NEXT: .LBB0_8: # %bb3
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; RV64I-MEDIUM-NEXT: addi a0, zero, 2
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; RV64I-MEDIUM-NEXT: .LBB0_9: # %exit
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; RV64I-MEDIUM-NEXT: sw a0, 0(a1)
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; RV64I-MEDIUM-NEXT: .LBB0_10: # %exit
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; RV64I-MEDIUM-NEXT: ret
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entry:
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switch i32 %in, label %exit [
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i32 1, label %bb1
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@ -56,3 +162,178 @@ bb4:
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exit:
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ret void
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}
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define void @above_threshold(i32 %in, i32* %out) nounwind {
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; RV32I-SMALL-LABEL: above_threshold:
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; RV32I-SMALL: # %bb.0: # %entry
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; RV32I-SMALL-NEXT: addi a0, a0, -1
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; RV32I-SMALL-NEXT: addi a2, zero, 5
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; RV32I-SMALL-NEXT: bltu a2, a0, .LBB1_9
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; RV32I-SMALL-NEXT: # %bb.1: # %entry
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; RV32I-SMALL-NEXT: slli a0, a0, 2
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; RV32I-SMALL-NEXT: lui a2, %hi(.LJTI1_0)
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; RV32I-SMALL-NEXT: addi a2, a2, %lo(.LJTI1_0)
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; RV32I-SMALL-NEXT: add a0, a0, a2
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; RV32I-SMALL-NEXT: lw a0, 0(a0)
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; RV32I-SMALL-NEXT: jr a0
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; RV32I-SMALL-NEXT: .LBB1_2: # %bb1
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; RV32I-SMALL-NEXT: addi a0, zero, 4
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; RV32I-SMALL-NEXT: j .LBB1_8
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; RV32I-SMALL-NEXT: .LBB1_3: # %bb2
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; RV32I-SMALL-NEXT: addi a0, zero, 3
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; RV32I-SMALL-NEXT: j .LBB1_8
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; RV32I-SMALL-NEXT: .LBB1_4: # %bb3
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; RV32I-SMALL-NEXT: addi a0, zero, 2
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; RV32I-SMALL-NEXT: j .LBB1_8
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; RV32I-SMALL-NEXT: .LBB1_5: # %bb4
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; RV32I-SMALL-NEXT: addi a0, zero, 1
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; RV32I-SMALL-NEXT: j .LBB1_8
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; RV32I-SMALL-NEXT: .LBB1_6: # %bb5
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; RV32I-SMALL-NEXT: addi a0, zero, 100
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; RV32I-SMALL-NEXT: j .LBB1_8
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; RV32I-SMALL-NEXT: .LBB1_7: # %bb6
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; RV32I-SMALL-NEXT: addi a0, zero, 200
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; RV32I-SMALL-NEXT: .LBB1_8: # %exit
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; RV32I-SMALL-NEXT: sw a0, 0(a1)
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; RV32I-SMALL-NEXT: .LBB1_9: # %exit
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; RV32I-SMALL-NEXT: ret
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;
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; RV32I-MEDIUM-LABEL: above_threshold:
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; RV32I-MEDIUM: # %bb.0: # %entry
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; RV32I-MEDIUM-NEXT: addi a0, a0, -1
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; RV32I-MEDIUM-NEXT: addi a2, zero, 5
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; RV32I-MEDIUM-NEXT: bltu a2, a0, .LBB1_9
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; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
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; RV32I-MEDIUM-NEXT: slli a0, a0, 2
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; RV32I-MEDIUM-NEXT: .LBB1_10: # %entry
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; RV32I-MEDIUM-NEXT: # Label of block must be emitted
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; RV32I-MEDIUM-NEXT: auipc a2, %pcrel_hi(.LJTI1_0)
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; RV32I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.LBB1_10)
|
||||
; RV32I-MEDIUM-NEXT: add a0, a0, a2
|
||||
; RV32I-MEDIUM-NEXT: lw a0, 0(a0)
|
||||
; RV32I-MEDIUM-NEXT: jr a0
|
||||
; RV32I-MEDIUM-NEXT: .LBB1_2: # %bb1
|
||||
; RV32I-MEDIUM-NEXT: addi a0, zero, 4
|
||||
; RV32I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV32I-MEDIUM-NEXT: .LBB1_3: # %bb2
|
||||
; RV32I-MEDIUM-NEXT: addi a0, zero, 3
|
||||
; RV32I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV32I-MEDIUM-NEXT: .LBB1_4: # %bb3
|
||||
; RV32I-MEDIUM-NEXT: addi a0, zero, 2
|
||||
; RV32I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV32I-MEDIUM-NEXT: .LBB1_5: # %bb4
|
||||
; RV32I-MEDIUM-NEXT: addi a0, zero, 1
|
||||
; RV32I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV32I-MEDIUM-NEXT: .LBB1_6: # %bb5
|
||||
; RV32I-MEDIUM-NEXT: addi a0, zero, 100
|
||||
; RV32I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV32I-MEDIUM-NEXT: .LBB1_7: # %bb6
|
||||
; RV32I-MEDIUM-NEXT: addi a0, zero, 200
|
||||
; RV32I-MEDIUM-NEXT: .LBB1_8: # %exit
|
||||
; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
|
||||
; RV32I-MEDIUM-NEXT: .LBB1_9: # %exit
|
||||
; RV32I-MEDIUM-NEXT: ret
|
||||
;
|
||||
; RV64I-SMALL-LABEL: above_threshold:
|
||||
; RV64I-SMALL: # %bb.0: # %entry
|
||||
; RV64I-SMALL-NEXT: slli a0, a0, 32
|
||||
; RV64I-SMALL-NEXT: srli a0, a0, 32
|
||||
; RV64I-SMALL-NEXT: addi a0, a0, -1
|
||||
; RV64I-SMALL-NEXT: addi a2, zero, 5
|
||||
; RV64I-SMALL-NEXT: bltu a2, a0, .LBB1_9
|
||||
; RV64I-SMALL-NEXT: # %bb.1: # %entry
|
||||
; RV64I-SMALL-NEXT: slli a0, a0, 3
|
||||
; RV64I-SMALL-NEXT: lui a2, %hi(.LJTI1_0)
|
||||
; RV64I-SMALL-NEXT: addi a2, a2, %lo(.LJTI1_0)
|
||||
; RV64I-SMALL-NEXT: add a0, a0, a2
|
||||
; RV64I-SMALL-NEXT: ld a0, 0(a0)
|
||||
; RV64I-SMALL-NEXT: jr a0
|
||||
; RV64I-SMALL-NEXT: .LBB1_2: # %bb1
|
||||
; RV64I-SMALL-NEXT: addi a0, zero, 4
|
||||
; RV64I-SMALL-NEXT: j .LBB1_8
|
||||
; RV64I-SMALL-NEXT: .LBB1_3: # %bb2
|
||||
; RV64I-SMALL-NEXT: addi a0, zero, 3
|
||||
; RV64I-SMALL-NEXT: j .LBB1_8
|
||||
; RV64I-SMALL-NEXT: .LBB1_4: # %bb3
|
||||
; RV64I-SMALL-NEXT: addi a0, zero, 2
|
||||
; RV64I-SMALL-NEXT: j .LBB1_8
|
||||
; RV64I-SMALL-NEXT: .LBB1_5: # %bb4
|
||||
; RV64I-SMALL-NEXT: addi a0, zero, 1
|
||||
; RV64I-SMALL-NEXT: j .LBB1_8
|
||||
; RV64I-SMALL-NEXT: .LBB1_6: # %bb5
|
||||
; RV64I-SMALL-NEXT: addi a0, zero, 100
|
||||
; RV64I-SMALL-NEXT: j .LBB1_8
|
||||
; RV64I-SMALL-NEXT: .LBB1_7: # %bb6
|
||||
; RV64I-SMALL-NEXT: addi a0, zero, 200
|
||||
; RV64I-SMALL-NEXT: .LBB1_8: # %exit
|
||||
; RV64I-SMALL-NEXT: sw a0, 0(a1)
|
||||
; RV64I-SMALL-NEXT: .LBB1_9: # %exit
|
||||
; RV64I-SMALL-NEXT: ret
|
||||
;
|
||||
; RV64I-MEDIUM-LABEL: above_threshold:
|
||||
; RV64I-MEDIUM: # %bb.0: # %entry
|
||||
; RV64I-MEDIUM-NEXT: slli a0, a0, 32
|
||||
; RV64I-MEDIUM-NEXT: srli a0, a0, 32
|
||||
; RV64I-MEDIUM-NEXT: addi a0, a0, -1
|
||||
; RV64I-MEDIUM-NEXT: addi a2, zero, 5
|
||||
; RV64I-MEDIUM-NEXT: bltu a2, a0, .LBB1_9
|
||||
; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
|
||||
; RV64I-MEDIUM-NEXT: slli a0, a0, 3
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_10: # %entry
|
||||
; RV64I-MEDIUM-NEXT: # Label of block must be emitted
|
||||
; RV64I-MEDIUM-NEXT: auipc a2, %pcrel_hi(.LJTI1_0)
|
||||
; RV64I-MEDIUM-NEXT: addi a2, a2, %pcrel_lo(.LBB1_10)
|
||||
; RV64I-MEDIUM-NEXT: add a0, a0, a2
|
||||
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
|
||||
; RV64I-MEDIUM-NEXT: jr a0
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_2: # %bb1
|
||||
; RV64I-MEDIUM-NEXT: addi a0, zero, 4
|
||||
; RV64I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_3: # %bb2
|
||||
; RV64I-MEDIUM-NEXT: addi a0, zero, 3
|
||||
; RV64I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_4: # %bb3
|
||||
; RV64I-MEDIUM-NEXT: addi a0, zero, 2
|
||||
; RV64I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_5: # %bb4
|
||||
; RV64I-MEDIUM-NEXT: addi a0, zero, 1
|
||||
; RV64I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_6: # %bb5
|
||||
; RV64I-MEDIUM-NEXT: addi a0, zero, 100
|
||||
; RV64I-MEDIUM-NEXT: j .LBB1_8
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_7: # %bb6
|
||||
; RV64I-MEDIUM-NEXT: addi a0, zero, 200
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_8: # %exit
|
||||
; RV64I-MEDIUM-NEXT: sw a0, 0(a1)
|
||||
; RV64I-MEDIUM-NEXT: .LBB1_9: # %exit
|
||||
; RV64I-MEDIUM-NEXT: ret
|
||||
entry:
|
||||
switch i32 %in, label %exit [
|
||||
i32 1, label %bb1
|
||||
i32 2, label %bb2
|
||||
i32 3, label %bb3
|
||||
i32 4, label %bb4
|
||||
i32 5, label %bb5
|
||||
i32 6, label %bb6
|
||||
]
|
||||
bb1:
|
||||
store i32 4, i32* %out
|
||||
br label %exit
|
||||
bb2:
|
||||
store i32 3, i32* %out
|
||||
br label %exit
|
||||
bb3:
|
||||
store i32 2, i32* %out
|
||||
br label %exit
|
||||
bb4:
|
||||
store i32 1, i32* %out
|
||||
br label %exit
|
||||
bb5:
|
||||
store i32 100, i32* %out
|
||||
br label %exit
|
||||
bb6:
|
||||
store i32 200, i32* %out
|
||||
br label %exit
|
||||
exit:
|
||||
ret void
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue