From 0529a8e2de9bbf2537bd636279d557a457b5fa65 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault@amd.com>
Date: Thu, 1 Mar 2018 20:56:21 +0000
Subject: [PATCH] AMDGPU/GlobalISel: Mark i32->i64 zext as legal

llvm-svn: 326481
---
 llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp     |  3 +++
 .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir    | 14 ++++++++++++++
 2 files changed, 17 insertions(+)
 create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir

diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index 4882cf4be8c1..adf263ee425d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -66,6 +66,9 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
 
   setAction({G_FMUL, S32}, Legal);
 
+  setAction({G_ZEXT, S64}, Legal);
+  setAction({G_ZEXT, 1, S32}, Legal);
+
   setAction({G_FPTOSI, S32}, Legal);
   setAction({G_FPTOSI, 1, S32}, Legal);
 
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
new file mode 100644
index 000000000000..1b32d60b9dce
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
@@ -0,0 +1,14 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer -global-isel %s -o - | FileCheck %s
+
+---
+name: test_zext_i32_to_i64
+body: |
+  bb.0.entry:
+    liveins: $vgpr0
+
+    ; CHECK-LABEL: name: test_zext_i32_to_i64
+    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s64) = G_ZEXT %0
+...