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[AMDGPU] getMemOperandsWithOffset: add resource operand for BUF instructions 

Summary:
This prevents unwanted clustering of BUF instructions with the same
vaddr but different resource descriptors.

Reviewers: rampitec, arsenm, nhaehnle

Subscribers: kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73867
This commit is contained in:
Jay Foad 2020-01-06 16:00:01 +00:00
parent b2e884bee7
commit 05297b7cbe
2 changed files with 8 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -331,26 +331,24 @@ bool SIInstrInfo::getMemOperandsWithOffset(
const MachineOperand *OffsetImm = const MachineOperand *OffsetImm =
getNamedOperand(LdSt, AMDGPU::OpName::offset); getNamedOperand(LdSt, AMDGPU::OpName::offset);
BaseOps.push_back(RSrc);
BaseOps.push_back(SOffset); BaseOps.push_back(SOffset);
Offset = OffsetImm->getImm(); Offset = OffsetImm->getImm();
return true; return true;
} }
const MachineOperand *AddrReg = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr);
if (!AddrReg) if (!BaseOp)
return false; return false;
const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc);
BaseOps.push_back(RSrc);
BaseOps.push_back(BaseOp);
const MachineOperand *OffsetImm = const MachineOperand *OffsetImm =
getNamedOperand(LdSt, AMDGPU::OpName::offset); getNamedOperand(LdSt, AMDGPU::OpName::offset);
BaseOp = AddrReg;
Offset = OffsetImm->getImm(); Offset = OffsetImm->getImm();
if (SOffset) // soffset can be an inline immediate. if (SOffset) // soffset can be an inline immediate.
Offset += SOffset->getImm(); Offset += SOffset->getImm();
if (!BaseOp->isReg())
return false;
BaseOps.push_back(BaseOp);
return true; return true;
} }

4
llvm/test/CodeGen/AMDGPU/smrd.ll
View File

@ -482,8 +482,8 @@ main_body:
; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting) ; SMRD load with a non-const non-uniform offset of > 4 dwords (requires splitting)
; GCN-LABEL: {{^}}smrd_load_nonconst2: ; GCN-LABEL: {{^}}smrd_load_nonconst2:
; SIVIGFX9_10: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; SIVIGFX9_10-DAG: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; SIVIGFX9_10: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; SIVIGFX9_10-DAG: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; CI: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; CI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen ; CI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
; GCN: s_endpgm ; GCN: s_endpgm