forked from OSchip/llvm-project
parent
4be3990f3b
commit
05220c9a0d
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@ -1456,13 +1456,26 @@ let Constraints = "$src1 = $dst" in {
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} // AddedComplexity
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} // Constraints = "$src1 = $dst"
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multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,
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Domain d> {
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def rr : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),
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!strconcat(asm, "\t{$src, $dst|$dst, $src}"),
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[(set GR32:$dst, (Int RC:$src))], d>;
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}
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// Mask creation
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def MOVMSKPSrr : PSI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
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"movmskps\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (int_x86_sse_movmsk_ps VR128:$src))]>;
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def MOVMSKPDrr : PDI<0x50, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
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"movmskpd\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (int_x86_sse2_movmsk_pd VR128:$src))]>;
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defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",
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SSEPackedSingle>, TB;
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defm MOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd, "movmskpd",
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SSEPackedDouble>, TB, OpSize;
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let isAsmParserOnly = 1 in {
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defm VMOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps,
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"movmskps", SSEPackedSingle>, VEX;
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defm VMOVMSKPD : sse12_extr_sign_mask<VR128, int_x86_sse2_movmsk_pd,
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"movmskpd", SSEPackedDouble>, OpSize,
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VEX;
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}
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// Prefetch intrinsic.
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def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
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@ -10517,3 +10517,12 @@
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// CHECK: vcmppd $3, -4(%ebx,%ecx,8), %xmm2, %xmm3
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// CHECK: encoding: [0xc5,0xe9,0xc2,0x5c,0xcb,0xfc,0x03]
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vcmpunordpd -4(%ebx,%ecx,8), %xmm2, %xmm3
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// CHECK: vmovmskps %xmm2, %eax
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// CHECK: encoding: [0xc5,0xf8,0x50,0xc2]
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vmovmskps %xmm2, %eax
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// CHECK: vmovmskpd %xmm2, %eax
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// CHECK: encoding: [0xc5,0xf9,0x50,0xc2]
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vmovmskpd %xmm2, %eax
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