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Thread LLVMContext through MVT and related parts of SDISel. 

llvm-svn: 75153
This commit is contained in:
Owen Anderson 2009-07-09 17:57:24 +00:00
parent 17973e684d
commit 0504e0a222
25 changed files with 131 additions and 101 deletions
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4
llvm/include/llvm/CodeGen/CallingConvLower.h
View File

@ -142,17 +142,19 @@ class CCState {
const TargetMachine &TM;
const TargetRegisterInfo &TRI;
SmallVector<CCValAssign, 16> &Locs;
LLVMContext *Context;
unsigned StackOffset;
SmallVector<uint32_t, 16> UsedRegs;
public:
CCState(unsigned CC, bool isVarArg, const TargetMachine &TM,
SmallVector<CCValAssign, 16> &locs);
SmallVector<CCValAssign, 16> &locs, LLVMContext *C);
void addLoc(const CCValAssign &V) {
Locs.push_back(V);
}
LLVMContext *getContext() const { return Context; }
const TargetMachine &getTarget() const { return TM; }
unsigned getCallingConv() const { return CallingConv; }
bool isVarArg() const { return IsVarArg; }

5
llvm/include/llvm/CodeGen/SelectionDAG.h
View File

@ -78,6 +78,7 @@ class SelectionDAG {
FunctionLoweringInfo &FLI;
MachineModuleInfo *MMI;
DwarfWriter *DW;
LLVMContext* Context;
/// EntryNode - The starting token.
SDNode EntryNode;
@ -125,7 +126,8 @@ public:
/// init - Prepare this SelectionDAG to process code in the given
/// MachineFunction.
///
void init(MachineFunction &mf, MachineModuleInfo *mmi, DwarfWriter *dw);
void init(MachineFunction &mf, MachineModuleInfo *mmi, DwarfWriter *dw,
LLVMContext* C);
/// clear - Clear state and free memory necessary to make this
/// SelectionDAG ready to process a new block.
@ -138,6 +140,7 @@ public:
FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; }
MachineModuleInfo *getMachineModuleInfo() const { return MMI; }
DwarfWriter *getDwarfWriter() const { return DW; }
LLVMContext *getContext() const {return Context; }
/// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using 'dot'.
///

3
llvm/include/llvm/CodeGen/ValueTypes.h
View File

@ -23,6 +23,7 @@
namespace llvm {
class Type;
class LLVMContext;
struct MVT { // MVT = Machine Value Type
public:
@ -487,7 +488,7 @@ namespace llvm {
/// getTypeForMVT - This method returns an LLVM type corresponding to the
/// specified MVT. For integer types, this returns an unsigned type. Note
/// that this will abort for types that cannot be represented.
const Type *getTypeForMVT() const;
const Type *getTypeForMVT(LLVMContext &Context) const;
/// getMVT - Return the value type corresponding to the specified type.
/// This returns all pointers as iPTR. If HandleUnknown is true, unknown

4
llvm/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
View File

@ -19,9 +19,9 @@
using namespace llvm;
CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm,
SmallVector<CCValAssign, 16> &locs)
SmallVector<CCValAssign, 16> &locs, LLVMContext *C)
: CallingConv(CC), IsVarArg(isVarArg), TM(tm),
TRI(*TM.getRegisterInfo()), Locs(locs) {
TRI(*TM.getRegisterInfo()), Locs(locs), Context(C) {
// No stack is used.
StackOffset = 0;

12
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -3660,7 +3660,7 @@ SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
unsigned Align = LD1->getAlignment();
unsigned NewAlign = TLI.getTargetData()->
getABITypeAlignment(VT.getTypeForMVT());
getABITypeAlignment(VT.getTypeForMVT(*DAG.getContext()));
if (NewAlign <= Align &&
(!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
@ -3718,7 +3718,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
(!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
unsigned Align = TLI.getTargetData()->
getABITypeAlignment(VT.getTypeForMVT());
getABITypeAlignment(VT.getTypeForMVT(*DAG.getContext()));
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
@ -4989,7 +4989,8 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) {
unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
if (NewAlign <
TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT()))
TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT(
*DAG.getContext())))
return SDValue();
SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
@ -5044,7 +5045,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) {
unsigned OrigAlign = ST->getAlignment();
MVT SVT = Value.getOperand(0).getValueType();
unsigned Align = TLI.getTargetData()->
getABITypeAlignment(SVT.getTypeForMVT());
getABITypeAlignment(SVT.getTypeForMVT(*DAG.getContext()));
if (Align <= OrigAlign &&
((!LegalOperations && !ST->isVolatile()) ||
TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
@ -5324,7 +5325,8 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// Check the resultant load doesn't need a higher alignment than the
// original load.
unsigned NewAlign =
TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT());
TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT(
*DAG.getContext()));
if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
return SDValue();

28
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -359,7 +359,7 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP,
// smaller type.
TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
TLI.ShouldShrinkFPConstant(OrigVT)) {
const Type *SType = SVT.getTypeForMVT();
const Type *SType = SVT.getTypeForMVT(*DAG.getContext());
LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
VT = SVT;
Extend = true;
@ -1106,7 +1106,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
getABITypeAlignment(LD->getMemoryVT().getTypeForMVT(
*DAG.getContext()));
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
TLI);
@ -1289,7 +1290,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
getABITypeAlignment(LD->getMemoryVT().getTypeForMVT(
*DAG.getContext()));
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG,
TLI);
@ -1367,7 +1369,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
getABITypeAlignment(ST->getMemoryVT().getTypeForMVT(
*DAG.getContext()));
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
TLI);
@ -1466,7 +1469,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
getABITypeAlignment(ST->getMemoryVT().getTypeForMVT(
*DAG.getContext()));
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
TLI);
@ -1728,7 +1732,7 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
// Create the stack frame object.
unsigned SrcAlign =
TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
getTypeForMVT());
getTypeForMVT(*DAG.getContext()));
SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
@ -1739,7 +1743,8 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
unsigned SlotSize = SlotVT.getSizeInBits();
unsigned DestSize = DestVT.getSizeInBits();
unsigned DestAlign =
TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT(
*DAG.getContext()));
// Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT.
@ -1833,7 +1838,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) {
CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
} else {
assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
const Type *OpNTy = OpVT.getTypeForMVT();
const Type *OpNTy = OpVT.getTypeForMVT(*DAG.getContext());
CV.push_back(UndefValue::get(OpNTy));
}
}
@ -1887,7 +1892,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
MVT ArgVT = Node->getOperand(i).getValueType();
const Type *ArgTy = ArgVT.getTypeForMVT();
const Type *ArgTy = ArgVT.getTypeForMVT(*DAG.getContext());
Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
@ -1897,7 +1902,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
TLI.getPointerTy());
// Splice the libcall in wherever FindInputOutputChains tells us to.
const Type *RetTy = Node->getValueType(0).getTypeForMVT();
const Type *RetTy = Node->getValueType(0).getTypeForMVT(*DAG.getContext());
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
0, CallingConv::C, false, Callee, Args, DAG,
@ -2386,7 +2391,8 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node,
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(TLI.getTargetData()->
getTypeAllocSize(VT.getTypeForMVT()),
getTypeAllocSize(VT.getTypeForMVT(
*DAG.getContext())),
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);

4
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -1008,7 +1008,7 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0; i != NumOps; ++i) {
Entry.Node = Ops[i];
Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
Entry.Ty = Entry.Node.getValueType().getTypeForMVT(*DAG.getContext());
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
Args.push_back(Entry);
@ -1016,7 +1016,7 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
TLI.getPointerTy());
const Type *RetTy = RetVT.getTypeForMVT();
const Type *RetTy = RetVT.getTypeForMVT(*DAG.getContext());
std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
false, 0, CallingConv::C, false, Callee, Args, DAG, dl);

3
llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
View File

@ -115,7 +115,8 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
// Create the stack frame object. Make sure it is aligned for both
// the source and expanded destination types.
unsigned Alignment =
TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForMVT());
TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForMVT(
*DAG.getContext()));
SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
const Value *SV = PseudoSourceValue::getFixedStack(SPFI);

3
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -664,7 +664,8 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo,
// so use a truncating store.
SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
unsigned Alignment =
TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT(
*DAG.getContext()));
Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
// Load the Lo part from the stack slot.

14
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -797,7 +797,7 @@ void SelectionDAG::VerifyNode(SDNode *N) {
unsigned SelectionDAG::getMVTAlignment(MVT VT) const {
const Type *Ty = VT == MVT::iPTR ?
PointerType::get(Type::Int8Ty, 0) :
VT.getTypeForMVT();
VT.getTypeForMVT(*Context);
return TLI.getTargetData()->getABITypeAlignment(Ty);
}
@ -811,10 +811,11 @@ SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
}
void SelectionDAG::init(MachineFunction &mf, MachineModuleInfo *mmi,
DwarfWriter *dw) {
DwarfWriter *dw, LLVMContext* C) {
MF = &mf;
MMI = mmi;
DW = dw;
Context = C;
}
SelectionDAG::~SelectionDAG() {
@ -1387,7 +1388,7 @@ SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
unsigned ByteSize = VT.getStoreSizeInBits()/8;
const Type *Ty = VT.getTypeForMVT();
const Type *Ty = VT.getTypeForMVT(*Context);
unsigned StackAlign =
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
@ -1400,8 +1401,8 @@ SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) {
unsigned Bytes = std::max(VT1.getStoreSizeInBits(),
VT2.getStoreSizeInBits())/8;
const Type *Ty1 = VT1.getTypeForMVT();
const Type *Ty2 = VT2.getTypeForMVT();
const Type *Ty1 = VT1.getTypeForMVT(*Context);
const Type *Ty2 = VT2.getTypeForMVT(*Context);
const TargetData *TD = TLI.getTargetData();
unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1),
TD->getPrefTypeAlignment(Ty2));
@ -3099,7 +3100,8 @@ bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
if (VT != MVT::iAny) {
unsigned NewAlign = (unsigned)
TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT());
TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT(
*DAG.getContext()));
// If source is a string constant, this will require an unaligned load.
if (NewAlign > Align && (isSrcConst || AllowUnalign)) {
if (Dst.getOpcode() != ISD::FrameIndex) {

4
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
View File

@ -5520,7 +5520,7 @@ void TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
for (unsigned Value = 0, NumValues = ValueVTs.size();
Value != NumValues; ++Value) {
MVT VT = ValueVTs[Value];
const Type *ArgTy = VT.getTypeForMVT();
const Type *ArgTy = VT.getTypeForMVT(*DAG.getContext());
ISD::ArgFlagsTy Flags;
unsigned OriginalAlignment =
getTargetData()->getABITypeAlignment(ArgTy);
@ -5651,7 +5651,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
for (unsigned Value = 0, NumValues = ValueVTs.size();
Value != NumValues; ++Value) {
MVT VT = ValueVTs[Value];
const Type *ArgTy = VT.getTypeForMVT();
const Type *ArgTy = VT.getTypeForMVT(*DAG.getContext());
SDValue Op = SDValue(Args[i].Node.getNode(),
Args[i].Node.getResNo() + Value);
ISD::ArgFlagsTy Flags;

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -319,7 +319,7 @@ bool SelectionDAGISel::runOnFunction(Function &Fn) {
MachineModuleInfo *MMI = getAnalysisIfAvailable<MachineModuleInfo>();
DwarfWriter *DW = getAnalysisIfAvailable<DwarfWriter>();
CurDAG->init(*MF, MMI, DW);
CurDAG->init(*MF, MMI, DW, Context);
FuncInfo->set(Fn, *MF, *CurDAG, EnableFastISel);
SDL->init(GFI, *AA);

9
llvm/lib/Target/ARM/ARMISelLowering.cpp
View File

@ -695,7 +695,8 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
bool isVarArg = TheCall->isVarArg();
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
RVLocs, DAG.getContext());
CCInfo.AnalyzeCallResult(TheCall,
CCAssignFnForNode(CallingConv, /* Return*/ true));
@ -831,7 +832,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC, /* Return*/ false));
// Get a count of how many bytes are to be pushed on the stack.
@ -1032,7 +1033,7 @@ SDValue ARMTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
// CCState - Info about the registers and stack slots.
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
// Analyze return values of ISD::RET.
CCInfo.AnalyzeReturn(Op.getNode(), CCAssignFnForNode(CC, /* Return */ true));
@ -1384,7 +1385,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeFormalArguments(Op.getNode(),
CCAssignFnForNode(CC, /* Return*/ false));

7
llvm/lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -102,7 +102,7 @@ namespace {
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) {
MVT ArgVT = Op.getOperand(i).getValueType();
const Type *ArgTy = ArgVT.getTypeForMVT();
const Type *ArgTy = ArgVT.getTypeForMVT(*DAG.getContext());
Entry.Node = Op.getOperand(i);
Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
@ -113,7 +113,8 @@ namespace {
TLI.getPointerTy());
// Splice the libcall in wherever FindInputOutputChains tells us to.
const Type *RetTy = Op.getNode()->getValueType(0).getTypeForMVT();
const Type *RetTy =
Op.getNode()->getValueType(0).getTypeForMVT(*DAG.getContext());
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
0, CallingConv::C, false, Callee, Args, DAG,
@ -1336,7 +1337,7 @@ LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM) {
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
DebugLoc dl = Op.getDebugLoc();
CCState CCInfo(CC, isVarArg, TM, RVLocs);
CCState CCInfo(CC, isVarArg, TM, RVLocs, DAG.getContext());
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU);
// If this is the first return lowered for this function, add the regs to the

9
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
View File

@ -179,7 +179,7 @@ SDValue MSP430TargetLowering::LowerCCCArguments(SDValue Op,
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MSP430);
assert(!isVarArg && "Varargs not supported yet");
@ -256,7 +256,7 @@ SDValue MSP430TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// CCState - Info about the registers and stack slot.
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
// Analize return values of ISD::RET
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_MSP430);
@ -308,7 +308,7 @@ SDValue MSP430TargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeCallOperands(TheCall, CC_MSP430);
@ -435,7 +435,8 @@ MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
RVLocs, DAG.getContext());
CCInfo.AnalyzeCallResult(TheCall, RetCC_MSP430);
SmallVector<SDValue, 8> ResultVals;

9
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -721,7 +721,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG)
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
// To meet O32 ABI, Mips must always allocate 16 bytes on
// the stack (even if less than 4 are used as arguments)
@ -904,7 +904,8 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
RVLocs, DAG.getContext());
CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
SmallVector<SDValue, 8> ResultVals;
@ -948,7 +949,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG)
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
if (Subtarget->isABI_O32())
CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_MipsO32);
@ -1096,7 +1097,7 @@ LowerRET(SDValue Op, SelectionDAG &DAG)
DebugLoc dl = Op.getDebugLoc();
// CCState - Info about the registers and stack slot.
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
// Analize return values of ISD::RET
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Mips);

4
llvm/lib/Target/PIC16/PIC16ISelLowering.cpp
View File

@ -390,14 +390,14 @@ PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call,
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0; i != NumOps; ++i) {
Entry.Node = Ops[i];
Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
Entry.Ty = Entry.Node.getValueType().getTypeForMVT(*DAG.getContext());
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
Args.push_back(Entry);
}
SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i8);
const Type *RetTy = RetVT.getTypeForMVT();
const Type *RetTy = RetVT.getTypeForMVT(*DAG.getContext());
std::pair<SDValue,SDValue> CallInfo =
LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
false, 0, CallingConv::C, false, Callee, Args, DAG, dl);

18
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1283,8 +1283,8 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
// Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
std::pair<SDValue, SDValue> CallResult =
LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
false, false, 0, CallingConv::C, false,
LowerCallTo(Chain, Op.getValueType().getTypeForMVT(*DAG.getContext()),
false, false, false, false, 0, CallingConv::C, false,
DAG.getExternalSymbol("__trampoline_setup", PtrVT),
Args, DAG, dl);
@ -1527,7 +1527,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS_SVR4(SDValue Op,
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
// Reserve space for the linkage area on the stack.
CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
@ -1585,7 +1585,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS_SVR4(SDValue Op,
// Aggregates passed by value are stored in the local variable space of the
// caller's stack frame, right above the parameter list area.
SmallVector<CCValAssign, 16> ByValArgLocs;
CCState CCByValInfo(CC, isVarArg, getTargetMachine(), ByValArgLocs);
CCState CCByValInfo(CC, isVarArg, getTargetMachine(),
ByValArgLocs, DAG.getContext());
// Reserve stack space for the allocations in CCInfo.
CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
@ -2454,7 +2455,7 @@ static SDValue LowerCallReturn(SDValue Op, SelectionDAG &DAG, TargetMachine &TM,
SmallVector<SDValue, 16> ResultVals;
SmallVector<CCValAssign, 16> RVLocs;
unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
CCState CCRetInfo(CallerCC, isVarArg, TM, RVLocs);
CCState CCRetInfo(CallerCC, isVarArg, TM, RVLocs, DAG.getContext());
CCRetInfo.AnalyzeCallResult(TheCall, RetCC_PPC);
// Copy all of the result registers out of their specified physreg.
@ -2560,7 +2561,7 @@ SDValue PPCTargetLowering::LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG,
// Assign locations to all of the outgoing arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
// Reserve space for the linkage area on the stack.
CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
@ -2600,7 +2601,8 @@ SDValue PPCTargetLowering::LowerCALL_SVR4(SDValue Op, SelectionDAG &DAG,
// Assign locations to all of the outgoing aggregate by value arguments.
SmallVector<CCValAssign, 16> ByValArgLocs;
CCState CCByValInfo(CC, isVarArg, getTargetMachine(), ByValArgLocs);
CCState CCByValInfo(CC, isVarArg, getTargetMachine(), ByValArgLocs,
DAG.getContext());
// Reserve stack space for the allocations in CCInfo.
CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
@ -3065,7 +3067,7 @@ SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
DebugLoc dl = Op.getDebugLoc();
CCState CCInfo(CC, isVarArg, TM, RVLocs);
CCState CCInfo(CC, isVarArg, TM, RVLocs, DAG.getContext());
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
// If this is the first return lowered for this function, add the regs to the

5
llvm/lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -39,7 +39,7 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
DebugLoc dl = Op.getDebugLoc();
// CCState - Info about the registers and stack slot.
CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs, DAG.getContext());
// Analize return values of ISD::RET
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
@ -459,7 +459,8 @@ static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(),
RVLocs, DAG.getContext());
RVInfo.AnalyzeCallResult(TheCall, RetCC_Sparc32);
SmallVector<SDValue, 8> ResultVals;

4
llvm/lib/Target/X86/X86FastISel.cpp
View File

@ -1242,7 +1242,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, false, TM, ArgLocs);
CCState CCInfo(CC, false, TM, ArgLocs, I->getParent()->getContext());
CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CCAssignFnForCall(CC));
// Get a count of how many bytes are to be pushed on the stack.
@ -1382,7 +1382,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
// Now handle call return value (if any).
if (RetVT.getSimpleVT() != MVT::isVoid) {
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CC, false, TM, RVLocs);
CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext());
CCInfo.AnalyzeCallResult(RetVT, RetCC_X86);
// Copy all of the result registers out of their specified physreg.

9
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -1048,7 +1048,7 @@ SDValue X86TargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
SmallVector<CCValAssign, 16> RVLocs;
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_X86);
// If this is the first return lowered for this function, add the regs to the
@ -1174,7 +1174,8 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
SmallVector<CCValAssign, 16> RVLocs;
bool isVarArg = TheCall->isVarArg();
bool Is64Bit = Subtarget->is64Bit();
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
RVLocs, DAG.getContext());
CCInfo.AnalyzeCallResult(TheCall, RetCC_X86);
SmallVector<SDValue, 8> ResultVals;
@ -1383,7 +1384,7 @@ X86TargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeFormalArguments(Op.getNode(), CCAssignFnForNode(CC));
SmallVector<SDValue, 8> ArgValues;
@ -1678,7 +1679,7 @@ SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeCallOperands(TheCall, CCAssignFnForNode(CC));
// Get a count of how many bytes are to be pushed on the stack.

9
llvm/lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -448,7 +448,7 @@ LowerCCCCallTo(SDValue Op, SelectionDAG &DAG, unsigned CC)
// Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
// The ABI dictates there should be one stack slot available to the callee
// on function entry (for saving lr).
@ -574,7 +574,8 @@ LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
// Assign locations to each value returned by this call.
SmallVector<CCValAssign, 16> RVLocs;
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CallingConv, isVarArg, getTargetMachine(),
RVLocs, DAG.getContext());
CCInfo.AnalyzeCallResult(TheCall, RetCC_XCore);
SmallVector<SDValue, 8> ResultVals;
@ -630,7 +631,7 @@ LowerCCCArguments(SDValue Op, SelectionDAG &DAG)
// Assign locations to all of the incoming arguments.
SmallVector<CCValAssign, 16> ArgLocs;
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs, DAG.getContext());
CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_XCore);
@ -747,7 +748,7 @@ LowerRET(SDValue Op, SelectionDAG &DAG)
DebugLoc dl = Op.getDebugLoc();
// CCState - Info about the registers and stack slot.
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs, DAG.getContext());
// Analize return values of ISD::RET
CCInfo.AnalyzeReturn(Op.getNode(), RetCC_XCore);

57
llvm/lib/VMCore/ValueTypes.cpp
View File

@ -13,20 +13,23 @@
#include "llvm/ADT/StringExtras.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/LLVMContext.h"
#include "llvm/Type.h"
#include "llvm/DerivedTypes.h"
using namespace llvm;
MVT MVT::getExtendedIntegerVT(unsigned BitWidth) {
MVT VT;
VT.LLVMTy = IntegerType::get(BitWidth);
VT.LLVMTy = getGlobalContext().getIntegerType(BitWidth);
assert(VT.isExtended() && "Type is not extended!");
return VT;
}
MVT MVT::getExtendedVectorVT(MVT VT, unsigned NumElements) {
MVT ResultVT;
ResultVT.LLVMTy = VectorType::get(VT.getTypeForMVT(), NumElements);
ResultVT.LLVMTy = getGlobalContext().getVectorType(
VT.getTypeForMVT(getGlobalContext()),
NumElements);
assert(ResultVT.isExtended() && "Type is not extended!");
return ResultVT;
}
@ -131,7 +134,7 @@ std::string MVT::getMVTString() const {
/// getTypeForMVT - This method returns an LLVM type corresponding to the
/// specified MVT. For integer types, this returns an unsigned type. Note
/// that this will abort for types that cannot be represented.
const Type *MVT::getTypeForMVT() const {
const Type *MVT::getTypeForMVT(LLVMContext &Context) const {
switch (V) {
default:
assert(isExtended() && "Type is not extended!");
@ -142,34 +145,34 @@ const Type *MVT::getTypeForMVT() const {
case MVT::i16: return Type::Int16Ty;
case MVT::i32: return Type::Int32Ty;
case MVT::i64: return Type::Int64Ty;
case MVT::i128: return IntegerType::get(128);
case MVT::i128: return Context.getIntegerType(128);
case MVT::f32: return Type::FloatTy;
case MVT::f64: return Type::DoubleTy;
case MVT::f80: return Type::X86_FP80Ty;
case MVT::f128: return Type::FP128Ty;
case MVT::ppcf128: return Type::PPC_FP128Ty;
case MVT::v2i8: return VectorType::get(Type::Int8Ty, 2);
case MVT::v4i8: return VectorType::get(Type::Int8Ty, 4);
case MVT::v8i8: return VectorType::get(Type::Int8Ty, 8);
case MVT::v16i8: return VectorType::get(Type::Int8Ty, 16);
case MVT::v32i8: return VectorType::get(Type::Int8Ty, 32);
case MVT::v2i16: return VectorType::get(Type::Int16Ty, 2);
case MVT::v4i16: return VectorType::get(Type::Int16Ty, 4);
case MVT::v8i16: return VectorType::get(Type::Int16Ty, 16);
case MVT::v16i16: return VectorType::get(Type::Int16Ty, 8);
case MVT::v2i32: return VectorType::get(Type::Int32Ty, 2);
case MVT::v3i32: return VectorType::get(Type::Int32Ty, 3);
case MVT::v4i32: return VectorType::get(Type::Int32Ty, 4);
case MVT::v8i32: return VectorType::get(Type::Int32Ty, 8);
case MVT::v1i64: return VectorType::get(Type::Int64Ty, 1);
case MVT::v2i64: return VectorType::get(Type::Int64Ty, 2);
case MVT::v4i64: return VectorType::get(Type::Int64Ty, 4);
case MVT::v2f32: return VectorType::get(Type::FloatTy, 2);
case MVT::v3f32: return VectorType::get(Type::FloatTy, 3);
case MVT::v4f32: return VectorType::get(Type::FloatTy, 4);
case MVT::v8f32: return VectorType::get(Type::FloatTy, 8);
case MVT::v2f64: return VectorType::get(Type::DoubleTy, 2);
case MVT::v4f64: return VectorType::get(Type::DoubleTy, 4);
case MVT::v2i8: return Context.getVectorType(Type::Int8Ty, 2);
case MVT::v4i8: return Context.getVectorType(Type::Int8Ty, 4);
case MVT::v8i8: return Context.getVectorType(Type::Int8Ty, 8);
case MVT::v16i8: return Context.getVectorType(Type::Int8Ty, 16);
case MVT::v32i8: return Context.getVectorType(Type::Int8Ty, 32);
case MVT::v2i16: return Context.getVectorType(Type::Int16Ty, 2);
case MVT::v4i16: return Context.getVectorType(Type::Int16Ty, 4);
case MVT::v8i16: return Context.getVectorType(Type::Int16Ty, 16);
case MVT::v16i16: return Context.getVectorType(Type::Int16Ty, 8);
case MVT::v2i32: return Context.getVectorType(Type::Int32Ty, 2);
case MVT::v3i32: return Context.getVectorType(Type::Int32Ty, 3);
case MVT::v4i32: return Context.getVectorType(Type::Int32Ty, 4);
case MVT::v8i32: return Context.getVectorType(Type::Int32Ty, 8);
case MVT::v1i64: return Context.getVectorType(Type::Int64Ty, 1);
case MVT::v2i64: return Context.getVectorType(Type::Int64Ty, 2);
case MVT::v4i64: return Context.getVectorType(Type::Int64Ty, 4);
case MVT::v2f32: return Context.getVectorType(Type::FloatTy, 2);
case MVT::v3f32: return Context.getVectorType(Type::FloatTy, 3);
case MVT::v4f32: return Context.getVectorType(Type::FloatTy, 4);
case MVT::v8f32: return Context.getVectorType(Type::FloatTy, 8);
case MVT::v2f64: return Context.getVectorType(Type::DoubleTy, 2);
case MVT::v4f64: return Context.getVectorType(Type::DoubleTy, 4);
}
}
@ -198,4 +201,4 @@ MVT MVT::getMVT(const Type *Ty, bool HandleUnknown){
VTy->getNumElements());
}
}
}
}

2
llvm/lib/VMCore/Verifier.cpp
View File

@ -1619,7 +1619,7 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty,
"vector elements!", F);
return false;
}
} else if (MVT((MVT::SimpleValueType)VT).getTypeForMVT() != EltTy) {
} else if (MVT((MVT::SimpleValueType)VT).getTypeForMVT(*Context) != EltTy) {
CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is wrong!", F);
return false;
} else if (EltTy != Ty) {

4
llvm/utils/TableGen/CallingConvEmitter.cpp
View File

@ -163,12 +163,12 @@ void CallingConvEmitter::EmitAction(Record *Action,
O << Size << ", ";
else
O << "\n" << IndentStr << " State.getTarget().getTargetData()"
"->getTypeAllocSize(LocVT.getTypeForMVT()), ";
"->getTypeAllocSize(LocVT.getTypeForMVT(*State.getContext())), ";
if (Align)
O << Align;
else
O << "\n" << IndentStr << " State.getTarget().getTargetData()"
"->getABITypeAlignment(LocVT.getTypeForMVT())";
"->getABITypeAlignment(LocVT.getTypeForMVT(*State.getContext()))";
O << ");\n" << IndentStr
<< "State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset"
<< Counter << ", LocVT, LocInfo));\n";