forked from OSchip/llvm-project
[AArch64] Add -mgeneral_regs_only option.
llvm-svn: 199904
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@ -1061,6 +1061,13 @@ are listed below.
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CRC instructions are enabled by default on ARMv8.
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.. option:: -mgeneral_regs_only
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Generate code which only uses the general purpose registers.
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This option restricts the generated code to use general registers
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only. This only applies to the AArch64 architecture.
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Controlling Size of Debug Information
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-------------------------------------
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@ -72,6 +72,7 @@ def m_Group : OptionGroup<"<m group>">, Group<CompileOnly_Group>;
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def m_x86_Features_Group : OptionGroup<"<m x86 features group>">, Group<m_Group>;
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def m_hexagon_Features_Group : OptionGroup<"<m hexagon features group>">, Group<m_Group>;
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def m_arm_Features_Group : OptionGroup<"<m arm features group>">, Group<m_Group>;
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def m_aarch64_Features_Group : OptionGroup<"<m aarch64 features group>">, Group<m_Group>;
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def m_ppc_Features_Group : OptionGroup<"<m ppc features group>">, Group<m_Group>;
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def u_Group : OptionGroup<"<u group>">;
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@ -1053,6 +1054,9 @@ def mcrc : Flag<["-"], "mcrc">, Group<m_arm_Features_Group>,
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def mnocrc : Flag<["-"], "mnocrc">, Group<m_arm_Features_Group>,
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HelpText<"Disallow use of CRC instructions (ARM only)">;
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def mgeneral_regs_only : Flag<["-"], "mgeneral_regs_only">, Group<m_aarch64_Features_Group>,
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HelpText<"Generate code which only uses the general purpose registers (AArch64 only)">;
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def mvsx : Flag<["-"], "mvsx">, Group<m_ppc_Features_Group>;
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def mno_vsx : Flag<["-"], "mno-vsx">, Group<m_ppc_Features_Group>;
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def mfprnd : Flag<["-"], "mfprnd">, Group<m_ppc_Features_Group>;
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@ -515,10 +515,6 @@ static void getAArch64FPUFeatures(const Driver &D, const Arg *A,
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Features.push_back("+crypto");
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} else if (FPU == "neon") {
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Features.push_back("+neon");
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} else if (FPU == "none") {
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Features.push_back("-fp-armv8");
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Features.push_back("-crypto");
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Features.push_back("-neon");
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} else
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D.Diag(diag::err_drv_clang_unsupported) << A->getAsString(Args);
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}
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@ -1438,6 +1434,12 @@ static void getAArch64TargetFeatures(const Driver &D, const ArgList &Args,
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// Honor -mfpu=.
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if (const Arg *A = Args.getLastArg(options::OPT_mfpu_EQ))
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getAArch64FPUFeatures(D, A, Args, Features);
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if (Args.getLastArg(options::OPT_mgeneral_regs_only)) {
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Features.push_back("-fp-armv8");
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Features.push_back("-crypto");
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Features.push_back("-neon");
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}
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}
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static void getTargetFeatures(const Driver &D, const llvm::Triple &Triple,
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@ -19,8 +19,3 @@
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// CHECK-CRYPTO-NEON-FP-ARMV8: "-target-feature" "+neon"
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// CHECK-CRYPTO-NEON-FP-ARMV8: "-target-feature" "+crypto"
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// RUN: %clang -target aarch64-linux-eabi -mfpu=none %s -### 2>&1 \
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// RUN: | FileCheck --check-prefix=CHECK-NO-FP %s
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// CHECK-NO-FP: "-target-feature" "-fp-armv8"
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// CHECK-NO-FP: "-target-feature" "-crypto"
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// CHECK-NO-FP: "-target-feature" "-neon"
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@ -0,0 +1,7 @@
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// Test the -mgeneral_regs_only option
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// RUN: %clang -target aarch64-linux-eabi -mgeneral_regs_only %s -### 2>&1 \
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// RUN: | FileCheck --check-prefix=CHECK-NO-FP %s
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// CHECK-NO-FP: "-target-feature" "-fp-armv8"
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// CHECK-NO-FP: "-target-feature" "-crypto"
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// CHECK-NO-FP: "-target-feature" "-neon"
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