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[RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive 

Reviewers: luismarques, asb, evandro

Reviewed By: asb, evandro

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77030
This commit is contained in:
Zakk Chen 2020-04-30 03:24:19 -07:00
parent 98d763ad05
commit 04b9a46c84
3 changed files with 11 additions and 13 deletions
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20
llvm/lib/Target/RISCV/RISCV.td
View File

@ -140,12 +140,12 @@ def HasStdExtB : Predicate<"Subtarget->hasStdExtB()">,
AssemblerPredicate<(all_of FeatureStdExtB),
"'B' (Bit Manipulation Instructions)">;
def FeatureRVCHints
: SubtargetFeature<"rvc-hints", "EnableRVCHintInstrs", "true",
"Enable RVC Hint Instructions.">;
def FeatureNoRVCHints
: SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
"Disable RVC Hint Instructions.">;
def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
AssemblerPredicate<(all_of FeatureRVCHints),
"RVC Hint Instructions">;
AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
"RVC Hint Instructions">;
def FeatureStdExtV
: SubtargetFeature<"experimental-v", "HasStdExtV", "true",
@ -207,15 +207,13 @@ include "RISCVSchedRocket64.td"
// RISC-V processors supported.
//===----------------------------------------------------------------------===//
def : ProcessorModel<"generic-rv32", NoSchedModel, [FeatureRVCHints]>;
def : ProcessorModel<"generic-rv32", NoSchedModel, []>;
def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit,
FeatureRVCHints]>;
def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>;
def : ProcessorModel<"rocket-rv32", Rocket32Model, [FeatureRVCHints]>;
def : ProcessorModel<"rocket-rv32", Rocket32Model, []>;
def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit,
FeatureRVCHints]>;
def : ProcessorModel<"rocket-rv64", Rocket64Model, [Feature64Bit]>;
//===----------------------------------------------------------------------===//

2
llvm/lib/Target/RISCV/RISCVSubtarget.h
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@ -54,7 +54,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
bool EnableRVCHintInstrs = false;
bool EnableRVCHintInstrs = true;
bool EnableSaveRestore = false;
unsigned XLen = 32;
MVT XLenVT = MVT::i32;

2
llvm/test/MC/RISCV/rv32c-invalid.s
View File

@ -1,4 +1,4 @@
# RUN: not llvm-mc -triple=riscv32 -mattr=+c -mattr=-rvc-hints < %s 2>&1 \
# RUN: not llvm-mc -triple=riscv32 -mattr=+c -mattr=+no-rvc-hints < %s 2>&1 \
# RUN: | FileCheck %s
## GPRC