diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
index 58562f99d5f4..e4b2a40fba65 100644
--- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -995,7 +995,7 @@ public:
   void addConstantUImmOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     uint64_t Imm = getConstantImm() - Offset;
-    Imm &= (1 << Bits) - 1;
+    Imm &= (1ULL << Bits) - 1;
     Imm += Offset;
     Imm += AdjustOffset;
     Inst.addOperand(MCOperand::createImm(Imm));
@@ -1093,7 +1093,8 @@ public:
   bool isRegIdx() const { return Kind == k_RegisterIndex; }
   bool isImm() const override { return Kind == k_Immediate; }
   bool isConstantImm() const {
-    return isImm() && isa<MCConstantExpr>(getImm());
+    int64_t Res;
+    return isImm() && getImm()->evaluateAsAbsolute(Res);
   }
   bool isConstantImmz() const {
     return isConstantImm() && getConstantImm() == 0;
@@ -1264,7 +1265,9 @@ public:
 
   int64_t getConstantImm() const {
     const MCExpr *Val = getImm();
-    return static_cast<const MCConstantExpr *>(Val)->getValue();
+    int64_t Value = 0;
+    (void)Val->evaluateAsAbsolute(Value);
+    return Value;
   }
 
   MipsOperand *getMemBase() const {
@@ -4051,6 +4054,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_SImm32_Relaxed:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected 32-bit signed immediate");
+  case Match_UImm32_Coerced:
+    return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
+                 "expected 32-bit immediate");
   case Match_MemSImm9:
     return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo),
                  "expected memory with 9-bit signed offset");
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
index b8d8aa0ce20f..d1c2079f06a2 100644
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -186,8 +186,6 @@ class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>;
 class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>;
 class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>;
 class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>;
-class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>;
-class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>;
 class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>;
 class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>;
 class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>;
@@ -198,8 +196,6 @@ class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>;
 class LW_MMR6_ENC : LOAD_WORD_FM_MMR6;
 class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6;
 class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>;
-class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>;
-class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>;
 class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>;
 class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>;
 class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0,
@@ -1118,14 +1114,6 @@ class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd,
                                                  II_SQRT_S, fsqrt>;
 class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd,
                                                  II_SQRT_D, fsqrt>;
-class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd,
-                                                  FGR32Opnd, II_TRUNC>;
-class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd,
-                                                  AFGR64Opnd, II_TRUNC>;
-class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd,
-                                                 FGR32Opnd, II_ROUND>;
-class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd,
-                                                 II_ROUND>;
 class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd,
                                                    FGR32Opnd, II_ROUND>;
 class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd,
@@ -1664,10 +1652,6 @@ def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC,
                   ISA_MICROMIPS32R6;
-def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC,
-                   ISA_MICROMIPS32R6;
-def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC,
-                   ISA_MICROMIPS32R6;
 def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6;
 def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6;
 def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6;
@@ -1708,9 +1692,6 @@ def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC,
 def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6;
 def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6;
 def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6;
-def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC,
-                   ISA_MICROMIPS32R6;
-def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6;
 def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC,
                   ISA_MICROMIPS32R6;
 def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6;
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
index ed92265e47f6..fc83761e409b 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFPU.td
@@ -141,6 +141,16 @@ let AdditionalPredicates = [InMicroMips] in {
                   MFC1_FM_MM<0x40>;
     def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>,
                   MFC1_FM_MM<0x60>;
+    def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd,
+                                    II_RECIP_S>,
+                     ROUND_W_FM_MM<0b0, 0b01001000>;
+    def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd,
+                                 II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>;
+    def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd,
+                                    II_RECIP_S>,
+                     ROUND_W_FM_MM<0b0, 0b00001000>;
+    def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd,
+                                 II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>;
   }
   let DecoderNamespace = "MicroMips",  DecoderMethod = "DecodeFMemMMR2" in {
     def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>,
diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td
index 6bbbd51a6382..ab7aa9dcdcae 100644
--- a/llvm/lib/Target/Mips/MipsInstrFPU.td
+++ b/llvm/lib/Target/Mips/MipsInstrFPU.td
@@ -284,6 +284,16 @@ defm CEIL_W  : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2;
 defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2;
 defm CVT_W   : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>;
 
+let AdditionalPredicates = [NotInMicroMips] in {
+  def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>,
+                ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2;
+  def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>,
+                ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2;
+  def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>,
+                ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2;
+  def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>,
+                ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2;
+}
 let DecoderNamespace = "Mips64" in {
   let AdditionalPredicates = [NotInMicroMips] in {
   def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>,
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 39b310746082..3f3885443f7a 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -300,6 +300,9 @@ class INSN_MIPS3_32_NOT_32R6_64R6 {
 // The portions of MIPS-III that were also added to MIPS32
 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
 
+// The portions of MIPS-IV that were also added to MIPS32.
+class INSN_MIPS4_32 { list <Predicate> InsnPredicates = [HasMips4_32]; }
+
 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
 // MIPS32r6 and MIPS64r6.
 class INSN_MIPS4_32_NOT_32R6_64R6 {
@@ -312,6 +315,11 @@ class INSN_MIPS4_32R2_NOT_32R6_64R6 {
   list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
 }
 
+// The portions of MIPS-IV that were also added to MIPS32r2.
+class INSN_MIPS4_32R2 {
+  list<Predicate> InsnPredicates = [HasMips4_32r2];
+}
+
 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
 // MIPS32r6 and MIPS64r6.
 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
@@ -459,6 +467,16 @@ class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
   let DiagnosticType = "UImm" # Bits;
 }
 
+// Generic case - only to support certain assembly pseudo instructions.
+class UImmAnyAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
+    : AsmOperandClass {
+  let Name = "ImmAny";
+  let RenderMethod = "addConstantUImmOperands<32>";
+  let PredicateMethod = "isSImm<" # Bits # ">";
+  let SuperClasses = Supers;
+  let DiagnosticType = "ImmAny";
+}
+
 // AsmOperandClasses require a strict ordering which is difficult to manage
 // as a hierarchy. Instead, we use a linear ordering and impose an order that
 // is in some places arbitrary.
@@ -482,8 +500,13 @@ class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []>
 //     uimm5 < uimm5_64, and uimm5 < vsplat_uimm5
 //   This is entirely arbitrary. We need an ordering and what we pick is
 //   unimportant since only one is possible for a given mnemonic.
+
+def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> {
+  let Name = "UImm32_Coerced";
+  let DiagnosticType = "UImm32_Coerced";
+}
 def SImm32RelaxedAsmOperandClass
-    : SImmAsmOperandClass<32, []> {
+    : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> {
   let Name = "SImm32_Relaxed";
   let PredicateMethod = "isAnyImm<32>";
   let DiagnosticType = "SImm32_Relaxed";
@@ -507,6 +530,8 @@ def UImm16RelaxedAsmOperandClass
   let PredicateMethod = "isAnyImm<16>";
   let DiagnosticType = "UImm16_Relaxed";
 }
+// FIXME: One of these should probably have UImm16AsmOperandClass as the
+//        superclass instead of UImm16RelaxedasmOPerandClass.
 def UImm16AsmOperandClass
     : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>;
 def SImm16RelaxedAsmOperandClass
@@ -864,6 +889,10 @@ def simm16_64 : Operand<i64> {
   let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass");
 }
 
+// like simm32 but coerces simm32 to uimm32.
+def uimm32_coerced : Operand<i32> {
+  let ParserMatchClass = !cast<AsmOperandClass>("UImm32CoercedAsmOperandClass");
+}
 // Like simm32 but coerces uimm32 to simm32.
 def simm32_relaxed : Operand<i32> {
   let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>";
@@ -2379,11 +2408,12 @@ def : MipsInstAlias<"sync",
 // Assembler Pseudo Instructions
 //===----------------------------------------------------------------------===//
 
-// We use i32imm on li/la to defer range checking to the assembler.
+// We use uimm32_coerced to accept a 33 bit signed number that is rendered into
+// a 32 bit number.
 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
   MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
                      !strconcat(instr_asm, "\t$rt, $imm32")> ;
-def LoadImm32 : LoadImmediate32<"li", i32imm, GPR32Opnd>;
+def LoadImm32 : LoadImmediate32<"li", uimm32_coerced, GPR32Opnd>;
 
 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
                            RegisterOperand RO> :
diff --git a/llvm/lib/Target/Mips/MipsSchedule.td b/llvm/lib/Target/Mips/MipsSchedule.td
index 76bd818a4f17..c0de59ba15f5 100644
--- a/llvm/lib/Target/Mips/MipsSchedule.td
+++ b/llvm/lib/Target/Mips/MipsSchedule.td
@@ -270,11 +270,15 @@ def II_ORI              : InstrItinClass;
 def II_POP              : InstrItinClass;
 def II_RDHWR            : InstrItinClass;
 def II_RESTORE          : InstrItinClass;
+def II_RECIP_S          : InstrItinClass;
+def II_RECIP_D          : InstrItinClass;
 def II_RINT_S           : InstrItinClass;
 def II_RINT_D           : InstrItinClass;
 def II_ROTR             : InstrItinClass;
 def II_ROTRV            : InstrItinClass;
 def II_ROUND            : InstrItinClass;
+def II_RSQRT_S          : InstrItinClass;
+def II_RSQRT_D          : InstrItinClass;
 def II_SAVE             : InstrItinClass;
 def II_SC               : InstrItinClass;
 def II_SCD              : InstrItinClass;
@@ -607,6 +611,10 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [
   InstrItinData<II_NMSUB_D         , [InstrStage<8,  [ALU]>]>,
   InstrItinData<II_DIV_S           , [InstrStage<23, [ALU]>]>,
   InstrItinData<II_DIV_D           , [InstrStage<36, [ALU]>]>,
+  InstrItinData<II_RECIP_D         , [InstrStage<25, [ALU]>]>,
+  InstrItinData<II_RECIP_S         , [InstrStage<13, [ALU]>]>,
+  InstrItinData<II_RSQRT_D         , [InstrStage<29, [ALU]>]>,
+  InstrItinData<II_RSQRT_S         , [InstrStage<14, [ALU]>]>,
   InstrItinData<II_RINT_D          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_RINT_S          , [InstrStage<1,  [ALU]>]>,
   InstrItinData<II_SQRT_S          , [InstrStage<54, [ALU]>]>,
diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
index 9712addff1a4..15a0401b781e 100644
--- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td
+++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td
@@ -440,6 +440,10 @@ def : ItinRW<[GenericWriteFPUDivD], [II_DIV_D]>;
 def : ItinRW<[GenericWriteFPUSqrtS], [II_SQRT_S]>;
 def : ItinRW<[GenericWriteFPUSqrtD], [II_SQRT_D]>;
 
+// rsqrt.[ds], recip.[ds]
+def : ItinRW<[GenericWriteFPURcpS], [II_RECIP_S, II_RSQRT_S]>;
+def : ItinRW<[GenericWriteFPURcpD], [II_RECIP_D, II_RSQRT_D]>;
+
 // MIPSR6
 // ======
 //
diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td
index 976e9f56affb..882a241d1426 100644
--- a/llvm/lib/Target/Mips/MipsScheduleP5600.td
+++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td
@@ -448,6 +448,9 @@ def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>;
 def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>;
 def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>;
 
+def : ItinRW<[P5600WriteFPURsqrtD], [II_RECIP_D, II_RSQRT_D]>;
+def : ItinRW<[P5600WriteFPURsqrtS], [II_RECIP_S, II_RSQRT_S]>;
+
 // fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd],
 // fsub.[wd]
 def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>;
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
index cc391934c5a3..84f498754cd1 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
@@ -195,3 +195,7 @@
 0xea 0xb8 0x40 0x00 # CHECK: sdc1 $f7, 64($10)
 0x46 0xb8 0x04 0x00 # CHECK: sdc1 $f2, 4($6)
 0x46 0x98 0x04 0x00 # CHECK: swc1 $f2, 4($6)
+0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6
+0x7e,0x54,0x3b,0x12 # CHECK: recip.s $f3, $f30
+0x5c,0x54,0x3b,0x42 # CHECK: rsqrt.d $f2, $f28
+0x88,0x54,0x3b,0x02 # CHECK: rsqrt.s $f4, $f8
diff --git a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
index 894ac6e048f2..3be26bb5b661 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
@@ -199,3 +199,7 @@
 0x00 0x64 0xcd 0x3c # CHECK: cfc2 $3, $4
 0x54 0xa6 0x18 0x3b # CHECK: ctc1 $5, $6
 0x00 0xe8 0xdd 0x3c # CHECK: ctc2 $7, $8
+0x56 0x46 0x52 0x3b # CHECK: recip.d $f18, $f6
+0x54 0x7e 0x12 0x3b # CHECK: recip.s $f3, $f30
+0x54 0x5c 0x42 0x3b # CHECK: rsqrt.d $f2, $f28
+0x54 0x88 0x02 0x3b # CHECK: rsqrt.s $f4, $f8
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
index 82a883557e87..5a374ac43cb6 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2-el.txt
@@ -135,8 +135,12 @@
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
index 7ee4f4bf7fa8..9935929a1cc2 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt
@@ -286,6 +286,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
index da8130c9f4c4..bc7ae8dd8391 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-xfail-mips32r2.txt
@@ -70,13 +70,9 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
index 37c14de4cb6a..96c7805e2165 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3-el.txt
@@ -129,10 +129,14 @@
 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
index 8e5c16b4a337..9be0189e6bfb 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt
@@ -283,6 +283,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
index 7623bba364fc..5d317edd4658 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-xfail-mips32r3.txt
@@ -70,13 +70,9 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
index b68089b0a078..072e17b6151b 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5-el.txt
@@ -131,8 +131,12 @@
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
index afe1b695dea5..ecb64ccdea26 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt
@@ -284,6 +284,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x4c 0x52 0xf2 0xa9 # CHECK: msub.d $f10, $f2, $f30, $f18
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
index 27f5498ea661..ed9bc08d72d4 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-xfail-mips32r5.txt
@@ -70,13 +70,9 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
 0x46 0x20 0x03 0x08 # CHECK: round.l.d $f12, $f0
 0x46 0x00 0x2e 0x08 # CHECK: round.l.s $f24, $f5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x46 0x20 0xb5 0x89 # CHECK: trunc.l.d $f22, $f22
 0x46 0x00 0xff 0x09 # CHECK: trunc.l.s $f28, $f31
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
index 34bfd769f2d3..271ff904f172 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6-el.txt
@@ -125,8 +125,12 @@
 0x14 0x10 0x24 0x46 # CHECK: seleqz.d $f0, $f2, $f4
 0x17 0x10 0x04 0x46 # CHECK: selnez.s $f0, $f2, $f4
 0x17 0x10 0x24 0x46 # CHECK: selnez.d $f0, $f2, $f4
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0x9b 0x20 0x00 0x46 # CHECK: class.s $f2, $f4
 0x9b 0x20 0x20 0x46 # CHECK: class.d $f2, $f4
 0x09 0x04 0x80 0x00 # CHECK: jr.hb $4
diff --git a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
index 7266848706d3..b796f48d566f 100644
--- a/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips32r6/valid-mips32r6.txt
@@ -134,6 +134,10 @@
 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x42 0x00 0x00 0x58 # CHECK: eretnc
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 8 but the disassembler currently emits 12
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
index 4a3d78cde553..64c350e45a87 100644
--- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt
@@ -155,11 +155,15 @@
 0x27 0x38 0x07 0x00 # CHECK: nor $7, $zero, $7
 0x25 0x60 0x1d 0x02 # CHECK: or $12, $16, $sp
 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
-0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5) 
+0x08 0x00 0xa1 0xcc # CHECK: pref 1, 8($5)
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
 0x8c 0x21 0x20 0x46 # CHECK: round.w.d $f6, $f4
 0xcc 0xe6 0x00 0x46 # CHECK: round.w.s $f27, $f28
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0x6f 0xb2 0xd6 0xa1 # CHECK: sb $22, -19857($14)
 0xd8 0x49 0x6f 0xe2 # CHECK: sc $15, 18904($19)
 0xcd 0xdf 0xaf 0xf3 # CHECK: scd $15, -8243($sp)
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
index f225d2cc220d..2635b6bca7db 100644
--- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt
@@ -257,3 +257,7 @@
 0xf5 0xbe 0x77 0x6e # CHECK: sdc1 $f30, 30574($13)
 0xfa 0x54 0x5a 0x75 # CHECK: sdc2 $20, 23157($18)
 0xfd 0x4c 0x16 0xcb # CHECK: sd $12, 5835($10)
+0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
index 3375bcf31404..1b669389e7b4 100644
--- a/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt
@@ -36,7 +36,3 @@
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
 0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30
 0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4
-0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
index 1cd7b0bcebab..eb531aad8829 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-el.txt
@@ -206,6 +206,10 @@
 0x10 0x00 0xa4 0xa8 # CHECK: swl $4, 16($5)
 0x10 0x00 0xe6 0xb8 # CHECK: swr $6, 16($7)
 0xcf 0x01 0x00 0x00 # CHECK: sync 7
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23
 0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31
 0x0d 0x73 0x20 0x46 # CHECK: trunc.w.d $f12, $f14
diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt
index dd97bcd5a1f8..bb6807a25daa 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64-xfail.txt
@@ -73,8 +73,4 @@
 0x46 0xdd 0xd0 0x6d # CHECK: plu.ps $f1, $f26, $f29
 0x46 0xda 0xf2 0x6e # CHECK: pul.ps $f9, $f30, $f26
 0x46 0xc2 0x4e 0x2f # CHECK: puu.ps $f24, $f9, $f2
-0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
-0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x41 # CHECK: sub.ps $f5, $f14, $f26
diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
index 5b5427db1e10..8a6bf0ce6132 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt
@@ -331,6 +331,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0xd5 # CHECK: recip.d $f19, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0xd6 # CHECK: rsqrt.d $f3, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
index 3f2b7615eb31..cc74ce95ae39 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2-el.txt
@@ -193,12 +193,16 @@
 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
index 5de751234c81..ab857a55c7bb 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt
@@ -363,6 +363,10 @@
 0x5d 0x40 0xfc 0x59 # CHECK: bgtzl $10, -3736
 0x46 0xa0 0x81 0x21 # CHECK: cvt.d.l $f4, $f16
 0x46 0xa0 0xf3 0xe0 # CHECK: cvt.s.l $f15, $f30
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x4c 0xa6 0x00 0x05 # CHECK: luxc1 $f0, $6($5)
 0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12
 0x4c 0xb8 0x20 0x0d # CHECK: suxc1 $f4, $24($5)
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
index cbc2eee3fe19..145dcacb1f59 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-xfail-mips64r2.txt
@@ -67,10 +67,6 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
index 7d59ef6d3e03..31618400d93f 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3-el.txt
@@ -190,12 +190,16 @@
 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
index 01c02ad82224..7dd8d64f5c09 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt
@@ -351,8 +351,12 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
-0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
-0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
+0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0
+0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
 0x4d 0xbb 0x0d 0xe0 # CHECK: madd.s $f23, $f13, $f1, $f27   
 0x51 0xd3 0x0c 0x40 # CHECK: beql $14, $19, 12548
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
index 8c58eb1c9e3b..74ae59669f5c 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-xfail-mips64r3.txt
@@ -67,10 +67,6 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
index ee6ad1c71945..5cc0aa6b7161 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5-el.txt
@@ -190,12 +190,16 @@
 0x78 0x98 0x04 0x4f # CHECK: nmsub.s $f1, $f24, $f19, $f4
 0x25 0x18 0x65 0x00 # CHECK: or $3, $3, $5
 0x67 0x45 0xc9 0x34 # CHECK: ori $9, $6, 17767
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0xc2 0x49 0x26 0x00 # CHECK: rotr $9, $6, 7
 0x46 0x48 0xe6 0x00 # CHECK: rotrv $9, $6, $7
 0x08 0x0b 0x20 0x46 # CHECK: round.l.d $f12, $f1
 0x48 0x2e 0x00 0x46 # CHECK: round.l.s $f25, $f5
 0x0c 0x73 0x20 0x46 # CHECK: round.w.d $f12, $f14
 0x8c 0x39 0x00 0x46 # CHECK: round.w.s $f6, $f7
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0xc6 0x23 0xa4 0xa0 # CHECK: sb $4, 9158($5)
 0x06 0x00 0xa4 0xa0 # CHECK: sb $4, 6($5)
 0xc6 0x23 0xe9 0xe0 # CHECK: sc $9, 9158($7)
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
index 12e5294d36da..f2467e8e4808 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt
@@ -351,6 +351,10 @@
 0x46 0x80 0x5e 0xa1 # CHECK: cvt.d.w $f26, $f11
 0x46 0x80 0x73 0x21 # CHECK: cvt.d.w $f12, $f14
 0x46 0x80 0x7d 0xa0 # CHECK: cvt.s.w $f22, $f15
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x48 0x20 0x50 0x00 # CHECK: dmfc2 $zero, $10, 0           
 0x48 0xa4 0x50 0x00 # CHECK: dmtc2 $4, $10, 0              
 0x4d 0x0c 0xe0 0x21 # CHECK: madd.d $f0, $f8, $f28, $f12    
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
index b8a98bdf73e7..2d02fca4b7c7 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-xfail-mips64r5.txt
@@ -67,10 +67,6 @@
 0x46 0xda 0xf2 0x2e # CHECK: pul.ps $f8, $f30, $f26
 0x46 0xc2 0x46 0x2f # CHECK: puu.ps $f24, $f8, $f2
 0x41 0x49 0x98 0x00 # CHECK: rdpgpr s3, t1
-0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
-0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
 0x02 0xa7 0x68 0x46 # CHECK: rorv t5, a3, s5
-0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
-0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x46 0xda 0x71 0x01 # CHECK: sub.ps $f4, $f14, $f26
 0x41 0xcd 0x00 0x00 # CHECK: wrpgpr zero, t5
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
index cda529624836..15821640ff39 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6-el.txt
@@ -156,8 +156,12 @@
 0x99 0x10 0x64 0x00 # CHECK: mulu $2, $3, $4
 0x04 0x00 0x42 0x34 # CHECK: ori $2, $2, 4
 0x35 0x04 0xa1 0x7c # CHECK: pref 1, 8($5)
+0x95 0x34 0x20 0x46 # CHECK: recip.d $f18, $f6
+0xd5 0xf0 0x00 0x46 # CHECK: recip.s $f3, $f30
 0x9a 0x20 0x20 0x46 # CHECK: rint.d $f2, $f4
 0x9a 0x20 0x00 0x46 # CHECK: rint.s $f2, $f4
+0x96 0xe0 0x20 0x46 # CHECK: rsqrt.d $f2, $f28
+0x16 0x41 0x00 0x46 # CHECK: rsqrt.s $f4, $f8
 0x26 0xec 0x6f 0x7e # CHECK: sc $15, -40($19)
 0xa7 0xe6 0xaf 0x7f # CHECK: scd $15, -51($sp)
 0x0e 0x00 0x00 0x00 # CHECK: sdbbp
diff --git a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
index 7be3fa71b1e4..066c3d4a2739 100644
--- a/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
+++ b/llvm/test/MC/Disassembler/Mips/mips64r6/valid-mips64r6.txt
@@ -153,6 +153,10 @@
 0x46 0xa4 0x18 0x8d # CHECK: cmp.sult.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8e # CHECK: cmp.sle.d $f2, $f3, $f4
 0x46 0xa4 0x18 0x8f # CHECK: cmp.sule.d $f2, $f3, $f4
+0x46 0x20 0x34 0x95 # CHECK: recip.d $f18, $f6
+0x46 0x00 0xf0 0xd5 # CHECK: recip.s $f3, $f30
+0x46 0x20 0xe0 0x96 # CHECK: rsqrt.d $f2, $f28
+0x46 0x00 0x41 0x16 # CHECK: rsqrt.s $f4, $f8
 0x42 0x00 0x00 0x58 # CHECK: eretnc
 # FIXME: The encode/decode functions are not inverses of each other.
 #        The immediate should be 8 but the disassembler currently emits 12
diff --git a/llvm/test/MC/Mips/macro-li-bad.s b/llvm/test/MC/Mips/macro-li-bad.s
index 8fe622066e9c..29eedce713ab 100644
--- a/llvm/test/MC/Mips/macro-li-bad.s
+++ b/llvm/test/MC/Mips/macro-li-bad.s
@@ -7,5 +7,5 @@
 
   .text
   li $5, 0x100000000
-  # 32-BIT: :[[@LINE-1]]:3: error: instruction requires a 32-bit immediate
-  # 64-BIT: :[[@LINE-2]]:3: error: instruction requires a 32-bit immediate
+  # 32-BIT: :[[@LINE-1]]:10: error: expected 32-bit immediate
+  # 64-BIT: :[[@LINE-2]]:10: error: expected 32-bit immediate
diff --git a/llvm/test/MC/Mips/macro-li.s b/llvm/test/MC/Mips/macro-li.s
index 88e013a854e2..6cdc11d70d25 100644
--- a/llvm/test/MC/Mips/macro-li.s
+++ b/llvm/test/MC/Mips/macro-li.s
@@ -65,3 +65,11 @@ li $5, 0xc0008000 # CHECK: lui $5, 49152        # encoding: [0x3c,0x05,0xc0,0x00
                   # CHECK: ori $5, $5, 32768    # encoding: [0x34,0xa5,0x80,0x00]
 li $5, 0x80008000 # CHECK: lui $5, 32768        # encoding: [0x3c,0x05,0x80,0x00]
                   # CHECK: ori $5, $5, 32768    # encoding: [0x34,0xa5,0x80,0x00]
+li $4, ~0xffffffff # CHECK; addiu $4, $zero, 0  # encoding: [0x24,0x04,0x00,0x00]
+li $4, ~0x80000001 # CHECK: lui $4, 32767       # encoding: [0x3c,0x04,0x7f,0xff]
+                   # CHECK: ori $4, $4, 65534   # encoding: [0x34,0x84,0xff,0xfe]
+li $4, ~0x80000000 # CHECK: lui $4, 32767       # encoding: [0x3c,0x04,0x7f,0xff]
+                   # CHECK: ori $4, $4, 65535   # encoding: [0x34,0x84,0xff,0xff]
+li $4, ~0x7fffffff # CHECK: lui $4, 32768       # encoding: [0x3c,0x04,0x80,0x00]
+li $4, ~0x00000001 # CHECK: addiu $4, $zero, -2 # encoding: [0x24,0x04,0xff,0xfe]
+li $4, ~0x00000000 # CHECK: addiu $4, $zero, -1 # encoding: [0x24,0x04,0xff,0xff]
diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s
index c6e83c122aed..2178faee6ce7 100644
--- a/llvm/test/MC/Mips/micromips/valid.s
+++ b/llvm/test/MC/Mips/micromips/valid.s
@@ -203,3 +203,7 @@ cfc1 $1, $2                 # CHECK: cfc1 $1, $2            # encoding: [0x54,0x
 cfc2 $3, $4                 # CHECK: cfc2 $3, $4            # encoding: [0x00,0x64,0xcd,0x3c]
 ctc1 $5, $6                 # CHECK: ctc1 $5, $6            # encoding: [0x54,0xa6,0x18,0x3b]
 ctc2 $7, $8                 # CHECK: ctc2 $7, $8            # encoding: [0x00,0xe8,0xdd,0x3c]
+recip.s $f2, $f4            # CHECK: recip.s $f2, $f4       # encoding: [0x54,0x44,0x12,0x3b]
+recip.d $f2, $f4            # CHECK: recip.d $f2, $f4       # encoding: [0x54,0x44,0x52,0x3b]
+rsqrt.s $f3, $f5            # CHECK: rsqrt.s $f3, $f5       # encoding: [0x54,0x65,0x02,0x3b]
+rsqrt.d $f2, $f4            # CHECK: rsqrt.d $f2, $f4       # encoding: [0x54,0x44,0x42,0x3b]
diff --git a/llvm/test/MC/Mips/mips32r2/valid-xfail.s b/llvm/test/MC/Mips/mips32r2/valid-xfail.s
index 5a61eb6cbfb7..6fab97f7a62a 100644
--- a/llvm/test/MC/Mips/mips32r2/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips32r2/valid-xfail.s
@@ -102,13 +102,9 @@
         pul.ps          $f9,$f30,$f26
         puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
         rorv            $13,$a3,$s5
         round.l.d       $f12,$f1
         round.l.s       $f25,$f5
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
         sbe             $s7,33($s1)
         sce             $sp,189($10)
         she             $24,105($v0)
diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s
index 6a5c6a0a5132..0ffddb0cdfea 100644
--- a/llvm/test/MC/Mips/mips32r2/valid.s
+++ b/llvm/test/MC/Mips/mips32r2/valid.s
@@ -167,11 +167,15 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
         rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips32r3/valid-xfail.s b/llvm/test/MC/Mips/mips32r3/valid-xfail.s
index defa388c4df2..a442beb6198a 100644
--- a/llvm/test/MC/Mips/mips32r3/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips32r3/valid-xfail.s
@@ -102,13 +102,9 @@
         pul.ps          $f9,$f30,$f26
         puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
         rorv            $13,$a3,$s5
         round.l.d       $f12,$f1
         round.l.s       $f25,$f5
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
         sbe             $s7,33($s1)
         sce             $sp,189($10)
         she             $24,105($v0)
diff --git a/llvm/test/MC/Mips/mips32r3/valid.s b/llvm/test/MC/Mips/mips32r3/valid.s
index 1505ccb22443..a05df83ac2d3 100644
--- a/llvm/test/MC/Mips/mips32r3/valid.s
+++ b/llvm/test/MC/Mips/mips32r3/valid.s
@@ -167,11 +167,15 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
         rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips32r5/valid-xfail.s b/llvm/test/MC/Mips/mips32r5/valid-xfail.s
index c1bf7a4b3a29..33ea7c46358f 100644
--- a/llvm/test/MC/Mips/mips32r5/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips32r5/valid-xfail.s
@@ -102,13 +102,9 @@
         pul.ps          $f9,$f30,$f26
         puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
         rorv            $13,$a3,$s5
         round.l.d       $f12,$f1
         round.l.s       $f25,$f5
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
         sbe             $s7,33($s1)
         sce             $sp,189($10)
         she             $24,105($v0)
diff --git a/llvm/test/MC/Mips/mips32r5/valid.s b/llvm/test/MC/Mips/mips32r5/valid.s
index b3dd775c5384..3100dd401d7b 100644
--- a/llvm/test/MC/Mips/mips32r5/valid.s
+++ b/llvm/test/MC/Mips/mips32r5/valid.s
@@ -168,11 +168,15 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
         rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips32r6/valid.s b/llvm/test/MC/Mips/mips32r6/valid.s
index cd90fcd279bb..bb4c7c577f1e 100644
--- a/llvm/test/MC/Mips/mips32r6/valid.s
+++ b/llvm/test/MC/Mips/mips32r6/valid.s
@@ -139,6 +139,8 @@ a:
                                  # CHECK-NEXT: .set  mips32r2
                                  # CHECK-NEXT: rdhwr $sp, $11
                                  # CHECK-NEXT: .set  pop      # encoding: [0x7c,0x1d,0x58,0x3b]
+        recip.d $f19,$f6         # CHECK: recip.d $f19, $f6   # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s $f3,$f30         # CHECK: recip.s $f3, $f30   # encoding: [0x46,0x00,0xf0,0xd5]
         s.s    $f2, 8($3)        # CHECK: swc1 $f2, 8($3)     # encoding: [0xe4,0x62,0x00,0x08]
         s.d    $f2, 8($3)        # CHECK: sdc1 $f2, 8($3)     # encoding: [0xf4,0x62,0x00,0x08]
         sel.d   $f0,$f1,$f2      # CHECK: sel.d $f0, $f1, $f2 # encoding: [0x46,0x22,0x08,0x10]
@@ -185,6 +187,8 @@ a:
         sc      $15,-40($s3)     # CHECK: sc $15, -40($19)       # encoding: [0x7e,0x6f,0xec,0x26]
         clo     $11,$a1          # CHECK: clo $11, $5            # encoding: [0x00,0xa0,0x58,0x51]
         clz     $sp,$gp          # CHECK: clz $sp, $gp           # encoding: [0x03,0x80,0xe8,0x50]
+        rsqrt.s $f0,$f4          # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d $f2,$f6          # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         sgt     $4, $5           # CHECK: slt $4, $5, $4         # encoding: [0x00,0xa4,0x20,0x2a]
         sgt     $4, $5, $6       # CHECK: slt $4, $6, $5         # encoding: [0x00,0xc5,0x20,0x2a]
         sgtu    $4, $5           # CHECK: sltu $4, $5, $4        # encoding: [0x00,0xa4,0x20,0x2b]
diff --git a/llvm/test/MC/Mips/mips4/valid-xfail.s b/llvm/test/MC/Mips/mips4/valid-xfail.s
index 9c647d151153..21129bb9dbc4 100644
--- a/llvm/test/MC/Mips/mips4/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips4/valid-xfail.s
@@ -35,7 +35,3 @@
         c.ult.s         $fcc7,$f24,$f10
         c.un.d          $fcc6,$f23,$f24
         c.un.s          $fcc1,$f30,$f4
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s
index 18b02234a71f..e9a7ae90dd5d 100644
--- a/llvm/test/MC/Mips/mips4/valid.s
+++ b/llvm/test/MC/Mips/mips4/valid.s
@@ -196,10 +196,14 @@ a:
         or        $12,$s0,$sp
         or        $2, 4                # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]
         pref      1, 8($5)             # CHECK: pref 1, 8($5)          # encoding: [0xcc,0xa1,0x00,0x08]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6      # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30      # encoding: [0x46,0x00,0xf0,0xd5]
         round.l.d $f12,$f1
         round.l.s $f25,$f5
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips5/valid-xfail.s b/llvm/test/MC/Mips/mips5/valid-xfail.s
index d76118950fc1..8517315780e0 100644
--- a/llvm/test/MC/Mips/mips5/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips5/valid-xfail.s
@@ -72,8 +72,4 @@
         plu.ps          $f1,$f26,$f29
         pul.ps          $f9,$f30,$f26
         puu.ps          $f24,$f9,$f2
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
         sub.ps          $f5,$f14,$f26
diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s
index 0661a4d4f80c..62b1b48c767f 100644
--- a/llvm/test/MC/Mips/mips5/valid.s
+++ b/llvm/test/MC/Mips/mips5/valid.s
@@ -197,10 +197,14 @@ a:
         or        $12,$s0,$sp
         or        $2, 4                # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]
         pref      1, 8($5)             # CHECK: pref 1, 8($5)          # encoding: [0xcc,0xa1,0x00,0x08]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6      # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30      # encoding: [0x46,0x00,0xf0,0xd5]
         round.l.d $f12,$f1
         round.l.s $f25,$f5
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips64/valid-xfail.s b/llvm/test/MC/Mips/mips64/valid-xfail.s
index 7d1eb9264e26..c7513bf5d7e1 100644
--- a/llvm/test/MC/Mips/mips64/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64/valid-xfail.s
@@ -79,8 +79,4 @@
         plu.ps          $f1,$f26,$f29
         pul.ps          $f9,$f30,$f26
         puu.ps          $f24,$f9,$f2
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
         sub.ps          $f5,$f14,$f26
diff --git a/llvm/test/MC/Mips/mips64/valid.s b/llvm/test/MC/Mips/mips64/valid.s
index dbcddda55563..6235b89e1824 100644
--- a/llvm/test/MC/Mips/mips64/valid.s
+++ b/llvm/test/MC/Mips/mips64/valid.s
@@ -213,10 +213,14 @@ a:
         or        $12,$s0,$sp
         or        $2, 4                # CHECK: ori $2, $2, 4          # encoding: [0x34,0x42,0x00,0x04]
         pref      1, 8($5)             # CHECK: pref 1, 8($5)          # encoding: [0xcc,0xa1,0x00,0x08]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6      # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30      # encoding: [0x46,0x00,0xf0,0xd5]
         round.l.d $f12,$f1
         round.l.s $f25,$f5
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
index bf17b35c446c..d55d1fb9a196 100644
--- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s
@@ -101,11 +101,7 @@
         pul.ps          $f9,$f30,$f26
         puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
         rorv            $13,$a3,$s5
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
         sbe             $s7,33($s1)
         sce             $sp,189($10)
         she             $24,105($v0)
diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s
index f5a7ca5a894e..43f6b73b68e8 100644
--- a/llvm/test/MC/Mips/mips64r2/valid.s
+++ b/llvm/test/MC/Mips/mips64r2/valid.s
@@ -234,6 +234,8 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
         rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
@@ -241,6 +243,8 @@ a:
         round.l.s $f25,$f5
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips64r3/valid-xfail.s b/llvm/test/MC/Mips/mips64r3/valid-xfail.s
index 7e94200dfd62..2f38e73e442b 100644
--- a/llvm/test/MC/Mips/mips64r3/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r3/valid-xfail.s
@@ -104,11 +104,7 @@
         pul.ps          $f9,$f30,$f26
         puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
         rorv            $13,$a3,$s5
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
         sbe             $s7,33($s1)
         sce             $sp,189($10)
         she             $24,105($v0)
diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s
index 0101b3a7fe27..e8a65abd9762 100644
--- a/llvm/test/MC/Mips/mips64r3/valid.s
+++ b/llvm/test/MC/Mips/mips64r3/valid.s
@@ -234,6 +234,8 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
         rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
@@ -241,6 +243,8 @@ a:
         round.l.s $f25,$f5
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips64r5/valid-xfail.s b/llvm/test/MC/Mips/mips64r5/valid-xfail.s
index b5ecdcbfb726..44ff4ee9fc0b 100644
--- a/llvm/test/MC/Mips/mips64r5/valid-xfail.s
+++ b/llvm/test/MC/Mips/mips64r5/valid-xfail.s
@@ -104,11 +104,7 @@
         pul.ps          $f9,$f30,$f26
         puu.ps          $f24,$f9,$f2
         rdpgpr          $s3,$9
-        recip.d         $f19,$f6
-        recip.s         $f3,$f30
         rorv            $13,$a3,$s5
-        rsqrt.d         $f3,$f28
-        rsqrt.s         $f4,$f8
         sbe             $s7,33($s1)
         sce             $sp,189($10)
         she             $24,105($v0)
diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s
index a11cee7e588a..392fe3f65666 100644
--- a/llvm/test/MC/Mips/mips64r5/valid.s
+++ b/llvm/test/MC/Mips/mips64r5/valid.s
@@ -235,6 +235,8 @@ a:
                                        # CHECK-NEXT: .set  mips32r2
                                        # CHECK-NEXT: rdhwr $sp, $11
                                        # CHECK-NEXT: .set  pop          # encoding: [0x7c,0x1d,0x58,0x3b]
+        recip.d   $f19,$f6             # CHECK: recip.d $f19, $f6       # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s   $f3,$f30             # CHECK: recip.s $f3, $f30       # encoding: [0x46,0x00,0xf0,0xd5]
         rotr      $1,15                # CHECK: rotr $1, $1, 15         # encoding: [0x00,0x21,0x0b,0xc2]
         rotr      $1,$14,15            # CHECK: rotr $1, $14, 15        # encoding: [0x00,0x2e,0x0b,0xc2]
         rotrv     $1,$14,$15           # CHECK: rotrv $1, $14, $15      # encoding: [0x01,0xee,0x08,0x46]
@@ -242,6 +244,8 @@ a:
         round.l.s $f25,$f5
         round.w.d $f6,$f4
         round.w.s $f27,$f28
+        rsqrt.s   $f0,$f4              # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d   $f2,$f6              # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s       $f2, 8($3)           # CHECK: swc1  $f2, 8($3)       # encoding: [0xe4,0x62,0x00,0x08]
         s.d       $f2, 8($3)           # CHECK: sdc1  $f2, 8($3)       # encoding: [0xf4,0x62,0x00,0x08]
         sb        $s6,-19857($14)
diff --git a/llvm/test/MC/Mips/mips64r6/valid.s b/llvm/test/MC/Mips/mips64r6/valid.s
index b92fd09f310d..7ad4dc3c3d21 100644
--- a/llvm/test/MC/Mips/mips64r6/valid.s
+++ b/llvm/test/MC/Mips/mips64r6/valid.s
@@ -194,8 +194,12 @@ a:
                                  # CHECK-NEXT: .set  mips32r2
                                  # CHECK-NEXT: rdhwr $sp, $11
                                  # CHECK-NEXT: .set  pop         # encoding: [0x7c,0x1d,0x58,0x3b]
+        recip.d $f19,$f6         # CHECK: recip.d $f19, $f6      # encoding: [0x46,0x20,0x34,0xd5]
+        recip.s $f3,$f30         # CHECK: recip.s $f3, $f30      # encoding: [0x46,0x00,0xf0,0xd5]
         rint.d $f2, $f4          # CHECK: rint.d $f2, $f4        # encoding: [0x46,0x20,0x20,0x9a]
         rint.s $f2, $f4          # CHECK: rint.s $f2, $f4        # encoding: [0x46,0x00,0x20,0x9a]
+        rsqrt.s $f0,$f4          # CHECK: rsqrt.s $f0, $f4       # encoding: [0x46,0x00,0x20,0x16]
+        rsqrt.d $f2,$f6          # CHECK: rsqrt.d $f2, $f6       # encoding: [0x46,0x20,0x30,0x96]
         s.s    $f2, 8($3)        # CHECK: swc1 $f2, 8($3)        # encoding: [0xe4,0x62,0x00,0x08]
         s.d    $f2, 8($3)        # CHECK: sdc1 $f2, 8($3)        # encoding: [0xf4,0x62,0x00,0x08]
         sc      $15,-40($s3)     # CHECK: sc $15, -40($19)       # encoding: [0x7e,0x6f,0xec,0x26]