forked from OSchip/llvm-project
[Powerpc] set instruction count as lsr first priority of lsr.
On Powerpc, set instruction count as lsr first priority of lsr by default. Add an option ppc-lsr-no-insns-cost to return back to default lsr cost model. Reviewed By: steven.zhang, jsji Differential Revision: https://reviews.llvm.org/D72683
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@ -33,6 +33,10 @@ EnablePPCColdCC("ppc-enable-coldcc", cl::Hidden, cl::init(false),
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cl::desc("Enable using coldcc calling conv for cold "
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"internal functions"));
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static cl::opt<bool>
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LsrNoInsnsCost("ppc-lsr-no-insns-cost", cl::Hidden, cl::init(false),
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cl::desc("Do not add instruction count to lsr cost model"));
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// The latency of mtctr is only justified if there are more than 4
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// comparisons that will be removed as a result.
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static cl::opt<unsigned>
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@ -967,3 +971,16 @@ bool PPCTTIImpl::canSaveCmp(Loop *L, BranchInst **BI, ScalarEvolution *SE,
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*BI = HWLoopInfo.ExitBranch;
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return true;
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}
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bool PPCTTIImpl::isLSRCostLess(TargetTransformInfo::LSRCost &C1,
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TargetTransformInfo::LSRCost &C2) {
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// PowerPC default behaviour here is "instruction number 1st priority".
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// If LsrNoInsnsCost is set, call default implementation.
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if (!LsrNoInsnsCost)
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return std::tie(C1.Insns, C1.NumRegs, C1.AddRecCost, C1.NumIVMuls,
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C1.NumBaseAdds, C1.ScaleCost, C1.ImmCost, C1.SetupCost) <
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std::tie(C2.Insns, C2.NumRegs, C2.AddRecCost, C2.NumIVMuls,
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C2.NumBaseAdds, C2.ScaleCost, C2.ImmCost, C2.SetupCost);
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else
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return TargetTransformInfoImplBase::isLSRCostLess(C1, C2);
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}
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@ -63,6 +63,8 @@ public:
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TargetLibraryInfo *LibInfo);
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP);
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bool isLSRCostLess(TargetTransformInfo::LSRCost &C1,
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TargetTransformInfo::LSRCost &C2);
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/// @}
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@ -17,9 +17,10 @@ entry:
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; CHECK-LABEL: @foo
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; CHECK: addi [[REG1:[0-9]+]], 1,
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; CHECK: addi [[REG2:[0-9]+]], 1,
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; CHECK: li [[REG3:[0-9]+]], 0
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; CHECK: %for.body.i
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; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG1]])
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; CHECK-DAG: lfs {{[0-9]+}}, 0([[REG2]])
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; CHECK-DAG: lfsx {{[0-9]+}}, [[REG1]], [[REG3]]
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; CHECK-DAG: lfsx {{[0-9]+}}, [[REG2]], [[REG3]]
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; CHECK: blr
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; PIP-LABEL: @foo
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@ -1,5 +1,7 @@
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs < %s \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=INST
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs -ppc-lsr-no-insns-cost=true \
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; RUN: < %s -mtriple=powerpc64le-unknown-linux-gnu | FileCheck %s -check-prefix=REG
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; void test(unsigned *a, unsigned *b, unsigned *c)
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; {
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@ -10,16 +12,25 @@
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; compile with -fno-unroll-loops
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define void @lsr-insts-cost(i32* %0, i32* %1, i32* %2) {
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; CHECK-LABEL: lsr-insts-cost
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; CHECK: .LBB0_4: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: lxvd2x vs34, 0, r3
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; CHECK-NEXT: lxvd2x vs35, 0, r4
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; CHECK-NEXT: addi r4, r4, 16
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; CHECK-NEXT: addi r3, r3, 16
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; CHECK-NEXT: vadduwm v2, v3, v2
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; CHECK-NEXT: stxvd2x vs34, 0, r5
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; CHECK-NEXT: addi r5, r5, 16
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; CHECK-NEXT: bdnz .LBB0_4
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; INST-LABEL: lsr-insts-cost
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; INST: .LBB0_4: # =>This Inner Loop Header: Depth=1
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; INST-NEXT: lxvd2x vs34, r3, r6
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; INST-NEXT: lxvd2x vs35, r4, r6
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; INST-NEXT: vadduwm v2, v3, v2
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; INST-NEXT: stxvd2x vs34, r5, r6
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; INST-NEXT: addi r6, r6, 16
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; INST-NEXT: bdnz .LBB0_4
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;
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; REG-LABEL: lsr-insts-cost
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; REG: .LBB0_4: # =>This Inner Loop Header: Depth=1
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; REG-NEXT: lxvd2x vs34, 0, r3
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; REG-NEXT: lxvd2x vs35, 0, r4
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; REG-NEXT: addi r4, r4, 16
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; REG-NEXT: addi r3, r3, 16
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; REG-NEXT: vadduwm v2, v3, v2
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; REG-NEXT: stxvd2x vs34, 0, r5
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; REG-NEXT: addi r5, r5, 16
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; REG-NEXT: bdnz .LBB0_4
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%4 = getelementptr i32, i32* %2, i64 1024
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%5 = getelementptr i32, i32* %0, i64 1024
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%6 = getelementptr i32, i32* %1, i64 1024
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@ -29,14 +29,15 @@ vector.body: ; preds = %vector.body, %vecto
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br i1 %10, label %for.end, label %vector.body
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; CHECK: @foo
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; CHECK-DAG: li [[C16:[0-9]+]], 16
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; CHECK-DAG: li [[C0:[0-9]+]], 0
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; CHECK-DAG: lvx [[CNST:[0-9]+]],
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; CHECK: .LBB0_1:
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; CHECK-DAG: lvx [[LD1:[0-9]+]], 0, [[C0:[0-9]+]]
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; CHECK-DAG: lvx [[LD2:[0-9]+]], [[C0]], [[C16]]
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; CHECK-DAG: lvsl [[MASK1:[0-9]+]], 0, [[C0]]
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; CHECK-DAG: vperm [[VR1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
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; CHECK-DAG: vaddfp {{[0-9]+}}, [[VR1]], [[CNST]]
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; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
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; CHECK-DAG: add [[B3:[0-9]+]], [[B1]], [[C0]]
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; CHECK-DAG: lvx [[LD1:[0-9]+]], [[B1]], [[C0]]
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; CHECK-DAG: lvx [[LD2:[0-9]+]], [[B3]],
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; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
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; CHECK-DAG: vaddfp {{[0-9]+}}, [[R1]], [[CNST]]
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; CHECK: blr
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for.end: ; preds = %vector.body
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