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[PowerPC] Guard XSRSP in P8 for FastISel 

This is exposed by enabling FastIsel on 64bit AIX.
We are generating XSRSP regardless of the arch,
which may be wrong when -mcpu=pwr7.

The fix is to guard the generation in P8 only.

Reviewed By: qiucf

Differential Revision: https://reviews.llvm.org/D109365
This commit is contained in:
Jinsong Ji 2021-09-07 15:16:36 +00:00
parent 61d8e27193
commit 042a6564d3
2 changed files with 12 additions and 7 deletions
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15
llvm/lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -987,15 +987,16 @@ bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
auto RC = MRI.getRegClass(SrcReg);
if (Subtarget->hasSPE()) {
DestReg = createResultReg(&PPC::GPRCRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::EFSCFD), DestReg)
.addReg(SrcReg);
} else if (isVSFRCRegClass(RC)) {
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::EFSCFD),
DestReg)
.addReg(SrcReg);
} else if (Subtarget->hasP8Vector() && isVSFRCRegClass(RC)) {
DestReg = createResultReg(&PPC::VSSRCRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::XSRSP), DestReg)
.addReg(SrcReg);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::XSRSP),
DestReg)
.addReg(SrcReg);
} else {
SrcReg = copyRegToRegClass(&PPC::F8RCRegClass, SrcReg);
DestReg = createResultReg(&PPC::F4RCRegClass);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(PPC::FRSP), DestReg)

4
llvm/test/CodeGen/PowerPC/fast-isel-rsp.ll
View File

@ -2,6 +2,10 @@
; RUN: -verify-machineinstrs | FileCheck %s --check-prefix=GENERIC
; RUN: llc -mcpu=ppc -mtriple=powerpc64le-unknown-unknown -O0 < %s \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: llc -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -O0 < %s \
; RUN: -verify-machineinstrs | FileCheck %s
define float @testRSP(double %x) {
entry: