forked from OSchip/llvm-project
Reapply "AMDGPU: Cleanup and fix SMRD offset handling"
This reverts commit 6a4acb9d80.
This commit is contained in:
Matt Arsenault
parent
ba1f3db4b0
commit
0426c2d07d
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@ -1771,26 +1771,31 @@ bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
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SDLoc SL(ByteOffsetNode);
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GCNSubtarget::Generation Gen = Subtarget->getGeneration();
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int64_t ByteOffset = C->getSExtValue();
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int64_t EncodedOffset = AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset);
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if (AMDGPU::isLegalSMRDImmOffset(*Subtarget, ByteOffset)) {
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Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
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uint64_t ByteOffset = C->getZExtValue();
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Optional<int64_t> EncodedOffset =
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AMDGPU::getSMRDEncodedOffset(*Subtarget, ByteOffset);
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if (EncodedOffset) {
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Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
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Imm = true;
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return true;
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}
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if (!isUInt<32>(EncodedOffset) || !isUInt<32>(ByteOffset))
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if (Gen == AMDGPUSubtarget::SEA_ISLANDS) {
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EncodedOffset =
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AMDGPU::getSMRDEncodedLiteralOffset32(*Subtarget, ByteOffset);
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if (EncodedOffset) {
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Offset = CurDAG->getTargetConstant(*EncodedOffset, SL, MVT::i32);
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return true;
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}
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}
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if (!isUInt<32>(ByteOffset) && !isInt<32>(ByteOffset))
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return false;
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if (Gen == AMDGPUSubtarget::SEA_ISLANDS && isUInt<32>(EncodedOffset)) {
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// 32-bit Immediates are supported on Sea Islands.
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Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
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} else {
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SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
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Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
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C32Bit), 0);
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}
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SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
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Offset = SDValue(
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CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32, C32Bit), 0);
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Imm = false;
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return true;
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}
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@ -2107,15 +2107,14 @@ AMDGPUInstructionSelector::selectSmrdImm(MachineOperand &Root) const {
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return None;
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const GEPInfo &GEPInfo = AddrInfo[0];
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if (!AMDGPU::isLegalSMRDImmOffset(STI, GEPInfo.Imm))
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Optional<int64_t> EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
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if (!EncodedImm)
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return None;
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unsigned PtrReg = GEPInfo.SgprParts[0];
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int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
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[=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); }
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}};
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}
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@ -2129,13 +2128,14 @@ AMDGPUInstructionSelector::selectSmrdImm32(MachineOperand &Root) const {
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const GEPInfo &GEPInfo = AddrInfo[0];
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unsigned PtrReg = GEPInfo.SgprParts[0];
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int64_t EncodedImm = AMDGPU::getSMRDEncodedOffset(STI, GEPInfo.Imm);
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if (!isUInt<32>(EncodedImm))
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Optional<int64_t> EncodedImm =
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AMDGPU::getSMRDEncodedLiteralOffset32(STI, GEPInfo.Imm);
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if (!EncodedImm)
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return None;
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return {{
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[=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
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[=](MachineInstrBuilder &MIB) { MIB.addImm(EncodedImm); }
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[=](MachineInstrBuilder &MIB) { MIB.addImm(*EncodedImm); }
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}};
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}
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@ -587,7 +587,7 @@ void SIFrameLowering::emitEntryFunctionScratchSetup(const GCNSubtarget &ST,
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16, 4);
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unsigned Offset = Fn.getCallingConv() == CallingConv::AMDGPU_CS ? 16 : 0;
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const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
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unsigned EncodedOffset = AMDGPU::getSMRDEncodedOffset(Subtarget, Offset);
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unsigned EncodedOffset = AMDGPU::convertSMRDOffsetUnits(Subtarget, Offset);
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BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
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.addReg(Rsrc01)
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.addImm(EncodedOffset) // offset
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@ -501,7 +501,7 @@ void SILoadStoreOptimizer::CombineInfo::setMI(MachineBasicBlock::iterator MI,
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: 4;
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break;
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case S_BUFFER_LOAD_IMM:
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EltSize = AMDGPU::getSMRDEncodedOffset(STM, 4);
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EltSize = AMDGPU::convertSMRDOffsetUnits(STM, 4);
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break;
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default:
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EltSize = 4;
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@ -1247,16 +1247,43 @@ static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
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return isGCN3Encoding(ST) || isGFX10(ST);
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}
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int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
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static bool isLegalSMRDEncodedImmOffset(const MCSubtargetInfo &ST,
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int64_t EncodedOffset) {
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return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset)
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: isUInt<8>(EncodedOffset);
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}
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static bool isDwordAligned(uint64_t ByteOffset) {
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return (ByteOffset & 3) == 0;
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}
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uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST,
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uint64_t ByteOffset) {
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if (hasSMEMByteOffset(ST))
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return ByteOffset;
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assert(isDwordAligned(ByteOffset));
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return ByteOffset >> 2;
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}
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bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
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int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
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return (hasSMEMByteOffset(ST)) ?
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isUInt<20>(EncodedOffset) : isUInt<8>(EncodedOffset);
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Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
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int64_t ByteOffset) {
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if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
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return None;
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int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
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return isLegalSMRDEncodedImmOffset(ST, EncodedOffset) ?
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Optional<int64_t>(EncodedOffset) : None;
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}
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Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
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int64_t ByteOffset) {
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if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
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return None;
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assert(isCI(ST));
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int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
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return isUInt<32>(EncodedOffset) ? Optional<int64_t>(EncodedOffset) : None;
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}
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// Given Imm, split it into the values to put into the SOffset and ImmOffset
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@ -648,9 +648,19 @@ bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
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bool isArgPassedInSGPR(const Argument *Arg);
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/// \returns The encoding that will be used for \p ByteOffset in the SMRD
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/// offset field.
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int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
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/// Convert \p ByteOffset to dwords if the subtarget uses dword SMRD immediate
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/// offsets.
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uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset);
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/// \returns The encoding that will be used for \p ByteOffset in the SMRD offset
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/// field, or None if it won't fit. This is useful on all subtargets.
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Optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
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int64_t ByteOffset);
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/// \return The encoding that can be used for a 32-bit literal offset in an SMRD
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/// instruction. This is only useful on CI.s
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Optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
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int64_t ByteOffset);
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/// \returns true if this offset is small enough to fit in the SMRD
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/// offset field. \p ByteOffset should be the offset in bytes and
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@ -788,8 +788,9 @@ body: |
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; GFX7-LABEL: name: load_constant_s32_from_4_gep_1048575
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; GFX7: liveins: $sgpr0_sgpr1
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; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 262143, 0, 0 :: (load 4, addrspace 4)
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; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]
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; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1048575
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; GFX7: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
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; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
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; GFX8-LABEL: name: load_constant_s32_from_4_gep_1048575
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; GFX8: liveins: $sgpr0_sgpr1
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; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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@ -872,8 +873,9 @@ body: |
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; GFX7-LABEL: name: load_constant_s32_from_4_gep_1073741823
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; GFX7: liveins: $sgpr0_sgpr1
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; GFX7: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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; GFX7: [[S_LOAD_DWORD_IMM_ci:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM_ci [[COPY]], 268435455, 0, 0 :: (load 4, addrspace 4)
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; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_IMM_ci]]
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; GFX7: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741823
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; GFX7: [[S_LOAD_DWORD_SGPR:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_SGPR [[COPY]], [[S_MOV_B32_]], 0, 0 :: (load 4, addrspace 4)
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; GFX7: $sgpr0 = COPY [[S_LOAD_DWORD_SGPR]]
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; GFX8-LABEL: name: load_constant_s32_from_4_gep_1073741823
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; GFX8: liveins: $sgpr0_sgpr1
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; GFX8: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
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@ -368,9 +368,16 @@ done:
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; GCN-LABEL: {{^}}test_sink_constant_max_32_bit_offset_i32:
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; GCN: s_and_saveexec_b64
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; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, -4{{$}}
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; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 3{{$}}
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; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, -4{{$}}
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; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 3{{$}}
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; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
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; VI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, -4{{$}}
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; VI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 3{{$}}
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; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
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; CI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xffffffff{{$}}
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; GCN: s_or_b64 exec, exec
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define amdgpu_kernel void @test_sink_constant_max_32_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
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entry:
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@ -1,9 +1,11 @@
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;RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
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; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI,SICI
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; RUN: llc < %s -march=amdgcn -mcpu=hawaii -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,CI,SICI
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; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
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;GCN-LABEL: {{^}}s_buffer_load_imm:
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;GCN-NOT: s_waitcnt;
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;SI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x1
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;CI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x1
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;VI: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x4
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define amdgpu_ps void @s_buffer_load_imm(<4 x i32> inreg %desc) {
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main_body:
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@ -38,6 +40,7 @@ main_body:
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;GCN-LABEL: {{^}}s_buffer_loadx2_imm:
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;GCN-NOT: s_waitcnt;
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;SI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x10
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;CI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x10
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;VI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x40
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define amdgpu_ps void @s_buffer_loadx2_imm(<4 x i32> inreg %desc) {
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main_body:
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@ -78,6 +81,7 @@ main_body:
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;GCN-LABEL: {{^}}s_buffer_loadx3_imm:
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;GCN-NOT: s_waitcnt;
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;SI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x10
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;CI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x10
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;VI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x40
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define amdgpu_ps void @s_buffer_loadx3_imm(<4 x i32> inreg %desc) {
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main_body:
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@ -107,6 +111,7 @@ main_body:
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;GCN-LABEL: {{^}}s_buffer_loadx3_index_divergent:
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;GCN-NOT: s_waitcnt;
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;SI: buffer_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
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;CI: buffer_load_dwordx3 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
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;VI: buffer_load_dwordx3 v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
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define amdgpu_ps void @s_buffer_loadx3_index_divergent(<4 x i32> inreg %desc, i32 %index) {
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main_body:
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@ -122,6 +127,7 @@ main_body:
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;GCN-LABEL: {{^}}s_buffer_loadx4_imm:
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;GCN-NOT: s_waitcnt;
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;SI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x32
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;CI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x32
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;VI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0xc8
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define amdgpu_ps void @s_buffer_loadx4_imm(<4 x i32> inreg %desc) {
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main_body:
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@ -168,6 +174,7 @@ main_body:
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;GCN-LABEL: {{^}}s_buffer_load_imm_mergex2:
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;GCN-NOT: s_waitcnt;
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;SI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x1
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;CI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x1
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;VI: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x4
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define amdgpu_ps void @s_buffer_load_imm_mergex2(<4 x i32> inreg %desc) {
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main_body:
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@ -182,6 +189,7 @@ main_body:
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;GCN-LABEL: {{^}}s_buffer_load_imm_mergex4:
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;GCN-NOT: s_waitcnt;
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;SI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x2
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;CI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x2
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;VI: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x8
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define amdgpu_ps void @s_buffer_load_imm_mergex4(<4 x i32> inreg %desc) {
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main_body:
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@ -236,6 +244,214 @@ bb1: ; preds = %main_body
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ret void
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}
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; GCN-LABEL: {{^}}s_buffer_load_imm_neg1:
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; GCN: s_mov_b32 [[K:s[0-9]+]], -1{{$}}
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; GCN: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
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define amdgpu_ps i32 @s_buffer_load_imm_neg1(<4 x i32> inreg %desc) {
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%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -1, i32 0)
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ret i32 %load
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}
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; GCN-LABEL: {{^}}s_buffer_load_imm_neg4:
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; SI: s_mov_b32 [[K:s[0-9]+]], -4{{$}}
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; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
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; CI: s_buffer_load_dword s0, s[0:3], 0x3fffffff{{$}}
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; VI: s_mov_b32 [[K:s[0-9]+]], -4{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_neg4(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -4, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_neg8:
|
||||
; SI: s_mov_b32 [[K:s[0-9]+]], -8{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x3ffffffe{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_neg8(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -8, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_bit31:
|
||||
; SI: s_brev_b32 [[K:s[0-9]+]], 1{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x20000000{{$}}
|
||||
|
||||
; VI: s_brev_b32 [[K:s[0-9]+]], 1{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_bit31(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -2147483648, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_bit30:
|
||||
; SI: s_mov_b32 [[K:s[0-9]+]], 2.0{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x10000000{{$}}
|
||||
|
||||
; VI: s_mov_b32 [[K:s[0-9]+]], 2.0{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_bit30(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1073741824, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_bit29:
|
||||
; SI: s_brev_b32 [[K:s[0-9]+]], 4{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x8000000{{$}}
|
||||
|
||||
; VI: s_brev_b32 [[K:s[0-9]+]], 4{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_bit29(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 536870912, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_bit21:
|
||||
; SI: s_mov_b32 [[K:s[0-9]+]], 0x200000{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x80000{{$}}
|
||||
|
||||
; VI: s_mov_b32 [[K:s[0-9]+]], 0x200000{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_bit21(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 2097152, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_bit20:
|
||||
; SI: s_mov_b32 [[K:s[0-9]+]], 0x100000{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x40000{{$}}
|
||||
|
||||
; VI: s_mov_b32 [[K:s[0-9]+]], 0x100000{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_bit20(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1048576, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_neg_bit20:
|
||||
; SI: s_mov_b32 [[K:s[0-9]+]], 0xfff00000{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x3ffc0000{{$}}
|
||||
|
||||
; VI: s_mov_b32 [[K:s[0-9]+]], 0xfff00000{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_neg_bit20(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -1048576, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_bit19:
|
||||
; SI: s_mov_b32 [[K:s[0-9]+]], 0x80000{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
|
||||
|
||||
; VI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_bit19(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 524288, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_neg_bit19:
|
||||
; SI: s_mov_b32 [[K:s[0-9]+]], 0xfff80000{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
|
||||
|
||||
; VI s_buffer_load_dword s0, s[0:3], 0x20000{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_neg_bit19(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 -524288, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_255:
|
||||
; SICI: s_movk_i32 [[K:s[0-9]+]], 0xff{{$}}
|
||||
; SICI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; VI: s_buffer_load_dword s0, s[0:3], 0xff{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_255(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 255, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_256:
|
||||
; SICI: s_buffer_load_dword s0, s[0:3], 0x40{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], 0x100{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_256(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 256, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_1016:
|
||||
; SICI: s_buffer_load_dword s0, s[0:3], 0xfe{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], 0x3f8{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_1016(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1016, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_1020:
|
||||
; SICI: s_buffer_load_dword s0, s[0:3], 0xff{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], 0x3fc{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_1020(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1020, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_1021:
|
||||
; SICI: s_movk_i32 [[K:s[0-9]+]], 0x3fd{{$}}
|
||||
; SICI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_1021(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1021, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_1024:
|
||||
; SI: s_movk_i32 [[K:s[0-9]+]], 0x400{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x100{{$}}
|
||||
|
||||
; VI: s_buffer_load_dword s0, s[0:3], 0x400{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_1024(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1024, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_1025:
|
||||
; SICI: s_movk_i32 [[K:s[0-9]+]], 0x401{{$}}
|
||||
; SICI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; VI: s_buffer_load_dword s0, s[0:3], 0x401{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_1025(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1025, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}s_buffer_load_imm_1028:
|
||||
; SI: s_movk_i32 [[K:s[0-9]+]], 0x400{{$}}
|
||||
; SI: s_buffer_load_dword s0, s[0:3], [[K]]{{$}}
|
||||
|
||||
; CI: s_buffer_load_dword s0, s[0:3], 0x100{{$}}
|
||||
; VI: s_buffer_load_dword s0, s[0:3], 0x400{{$}}
|
||||
define amdgpu_ps i32 @s_buffer_load_imm_1028(<4 x i32> inreg %desc) {
|
||||
%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 1024, i32 0)
|
||||
ret i32 %load
|
||||
}
|
||||
|
||||
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)
|
||||
declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32)
|
||||
declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32)
|
||||
|
|
|
|||
Loading…
Reference in New Issue