From 041dba6dece603bbae7f016c28fd5418a5addfe2 Mon Sep 17 00:00:00 2001
From: Owen Anderson <resistor@mac.com>
Date: Tue, 23 Aug 2011 17:37:32 +0000
Subject: [PATCH] Fix two more instances of mis-matched operand names breaking
 disassembly.  Found by randomized testing.

llvm-svn: 138337
---
 llvm/lib/Target/ARM/ARMInstrThumb2.td         | 12 ++++++------
 llvm/test/MC/Disassembler/ARM/thumb-tests.txt |  6 ++++++
 2 files changed, 12 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMInstrThumb2.td b/llvm/lib/Target/ARM/ARMInstrThumb2.td
index 90df7c6cd0d4..fe1e90717609 100644
--- a/llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ b/llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -809,9 +809,9 @@ multiclass T2I_cmp_irs<bits<4> opcod, string opc,
    }
    // register
    def rr : T2TwoRegCmp<
-                (outs), (ins GPR:$lhs, rGPR:$rhs), iir,
-                opc, ".w\t$lhs, $rhs",
-                [(opnode GPR:$lhs, rGPR:$rhs)]> {
+                (outs), (ins GPR:$Rn, rGPR:$Rm), iir,
+                opc, ".w\t$Rn, $Rm",
+                [(opnode GPR:$Rn, rGPR:$Rm)]> {
      let Inst{31-27} = 0b11101;
      let Inst{26-25} = 0b01;
      let Inst{24-21} = opcod;
@@ -1001,9 +1001,9 @@ class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode>
 
 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier.
 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode>
-  : T2TwoReg<(outs rGPR:$dst), (ins rGPR:$Rm, rot_imm:$rot),
-             IIC_iEXTr, opc, "\t$dst, $Rm$rot",
-            [(set rGPR:$dst, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
+  : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot),
+             IIC_iEXTr, opc, "\t$Rd, $Rm$rot",
+            [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>,
           Requires<[HasT2ExtractPack, IsThumb2]> {
   bits<2> rot;
   let Inst{31-27} = 0b11111;
diff --git a/llvm/test/MC/Disassembler/ARM/thumb-tests.txt b/llvm/test/MC/Disassembler/ARM/thumb-tests.txt
index d93e75e9f383..959c8cf7a25c 100644
--- a/llvm/test/MC/Disassembler/ARM/thumb-tests.txt
+++ b/llvm/test/MC/Disassembler/ARM/thumb-tests.txt
@@ -286,3 +286,9 @@
 
 # CHECK: smlad	r5, r12, r8, r11
 0x2c 0xfb 0x8 0xb5
+
+# CHECK: teq.w	r0, r11
+0x90 0xea 0xb 0x8f
+
+# CHECK: uxtb16	r9, r12, ror #16
+0x3f 0xfa 0xec 0xf9