forked from OSchip/llvm-project
Add instruction encodings / disassembly support for rus instructions.
llvm-svn: 170330
This commit is contained in:
Richard Osborne
parent
ec339f70d6
commit
041071c558
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@ -72,6 +72,9 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus Decode2RInstruction(MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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@ -87,6 +90,21 @@ static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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#include "XCoreGenDisassemblerTables.inc"
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static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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@ -101,6 +119,17 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder) {
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if (Val > 11)
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return MCDisassembler::Fail;
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static unsigned Values[] = {
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32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
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};
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Inst.addOperand(MCOperand::CreateImm(Values[Val]));
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return MCDisassembler::Success;
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}
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static DecodeStatus
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Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
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unsigned Combined = fieldFromInstruction(Insn, 6, 5) +
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@ -152,6 +181,43 @@ Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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return S;
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}
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static DecodeStatus
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DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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Inst.addOperand(MCOperand::CreateImm(Op2));
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}
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return S;
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}
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static DecodeStatus
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DecodeRUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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}
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return S;
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}
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static DecodeStatus
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DecodeRUSSrcDstBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
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const void *Decoder) {
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unsigned Op1, Op2;
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DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
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if (S == MCDisassembler::Success) {
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
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DecodeBitpOperand(Inst, Op2, Address, Decoder);
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}
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return S;
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}
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MCDisassembler::DecodeStatus
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XCoreDisassembler::getInstruction(MCInst &instr,
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uint64_t &Size,
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@ -92,8 +92,26 @@ class _FR2R<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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let DecoderMethod = "DecodeR2RInstruction";
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}
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class _FRUS<dag outs, dag ins, string asmstr, list<dag> pattern>
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class _FRUS<bits<6> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstXCore<2, outs, ins, asmstr, pattern> {
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let Inst{15-11} = opc{5-1};
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let Inst{4} = opc{0};
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let DecoderMethod = "DecodeRUSInstruction";
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}
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// RUS with bitp operand
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class _FRUSBitp<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _FRUS<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeRUSBitpInstruction";
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}
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// RUS with first operand as both a source and a destination and a bitp second
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// operand
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class _FRUSSrcDstBitp<bits<6> opc, dag outs, dag ins, string asmstr,
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list<dag> pattern>
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: _FRUS<opc, outs, ins, asmstr, pattern> {
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let DecoderMethod = "DecodeRUSSrcDstBitpInstruction";
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}
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class _FL2R<dag outs, dag ins, string asmstr, list<dag> pattern>
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@ -759,7 +759,8 @@ def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
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"neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
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let Constraints = "$src1 = $dst" in {
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def SEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
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def SEXT_rus :
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_FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
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"sext $dst, $src2",
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[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
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immBitp:$src2))]>;
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@ -769,7 +770,8 @@ def SEXT_2r :
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"sext $dst, $src2",
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[(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
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def ZEXT_rus : _FRUS<(outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
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def ZEXT_rus :
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_FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
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"zext $dst, $src2",
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[(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
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immBitp:$src2))]>;
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@ -786,15 +788,14 @@ def ANDNOT_2r :
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}
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let isReMaterializable = 1, neverHasSideEffects = 1 in
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def MKMSK_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$size),
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"mkmsk $dst, $size",
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[]>;
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def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
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"mkmsk $dst, $size", []>;
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def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
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"mkmsk $dst, $size",
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[(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
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def GETR_rus : _FRUS<(outs GRRegs:$dst), (ins i32imm:$type),
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def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
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"getr $dst, $type",
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[(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
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@ -810,7 +811,7 @@ def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
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"outct res[$r], $val",
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[(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
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def OUTCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
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def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
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"outct res[$r], $val",
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[(int_xcore_outct GRRegs:$r, immUs:$val)]>;
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@ -850,7 +851,7 @@ def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
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"chkct res[$r], $val",
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[(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
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def CHKCT_rus : _F2RUS<(outs), (ins GRRegs:$r, i32imm:$val),
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def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
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"chkct res[$r], $val",
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[(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
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@ -138,3 +138,23 @@
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# CHECK: sext r9, r1
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0x45 0x37
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# rus instructions
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# CHECK: chkct res[r1], 8
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0x34 0xcf
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# CHECK: getr r11, 2
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0x4e 0x87
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# CHECK: mkmsk r4, 24
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0x72 0xa7
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# CHECK: outct res[r3], r0
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0xcc 0x4e
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# CHECK: sext r8, 16
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0xb1 0x37
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# CHECK: zext r2, 32
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0xd8 0x46
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