forked from OSchip/llvm-project
[RISCV] Rerrange RISCVInstrInfoZB.td to better group related wthings. NFC
Especially placing W instructions/patterns near their non-W versions.
This commit is contained in:
Craig Topper
parent
72a005bf19
commit
0405ac0150
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@ -338,13 +338,39 @@ def SH3ADD : ALU_rr<0b0010000, 0b110, "sh3add">,
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Sched<[WriteSHXADD, ReadSHXADD, ReadSHXADD]>;
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} // Predicates = [HasStdExtZba]
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let Predicates = [HasStdExtZba, IsRV64] in {
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def SLLI_UW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">,
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Sched<[WriteShiftImm32, ReadShiftImm32]>;
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def ADD_UW : ALUW_rr<0b0000100, 0b000, "add.uw">,
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Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
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def SH1ADD_UW : ALUW_rr<0b0010000, 0b010, "sh1add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SH2ADD_UW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SH3ADD_UW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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} // Predicates = [HasStdExtZbb, IsRV64]
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let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
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def ROL : ALU_rr<0b0110000, 0b001, "rol">,
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Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
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def ROR : ALU_rr<0b0110000, 0b101, "ror">,
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Sched<[WriteRotateReg, ReadRotateReg, ReadRotateReg]>;
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def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
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Sched<[WriteRotateImm, ReadRotateImm]>;
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} // Predicates = [HasStdExtZbbOrZbpOrZbkb]
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
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def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
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Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
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def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
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Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
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def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
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Sched<[WriteRotateImm32, ReadRotateImm32]>;
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} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
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let Predicates = [HasStdExtZbs] in {
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def BCLR : ALU_rr<0b0100100, 0b001, "bclr">,
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Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
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@ -354,30 +380,7 @@ def BINV : ALU_rr<0b0110100, 0b001, "binv">,
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Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
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def BEXT : ALU_rr<0b0100100, 0b101, "bext">,
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Sched<[WriteSingleBit, ReadSingleBit, ReadSingleBit]>;
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} // Predicates = [HasStdExtZbs]
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let Predicates = [HasStdExtZbp] in {
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def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
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def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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// These instructions were named xperm.n and xperm.b in the last version of
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// the draft bit manipulation specification they were included in. However, we
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// use the mnemonics given to them in the ratified Zbkx extension.
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let Predicates = [HasStdExtZbpOrZbkx] in {
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def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
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def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
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} // Predicates = [HasStdExtZbpOrZbkx]
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let Predicates = [HasStdExtZbp] in {
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def XPERM_H : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZbbOrZbpOrZbkb] in
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def RORI : RVBShift_ri<0b01100, 0b101, OPC_OP_IMM, "rori">,
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Sched<[WriteRotateImm, ReadRotateImm]>;
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let Predicates = [HasStdExtZbs] in {
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def BCLRI : RVBShift_ri<0b01001, 0b001, OPC_OP_IMM, "bclri">,
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Sched<[WriteSingleBitImm, ReadSingleBitImm]>;
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def BSETI : RVBShift_ri<0b00101, 0b001, OPC_OP_IMM, "bseti">,
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@ -389,10 +392,42 @@ def BEXTI : RVBShift_ri<0b01001, 0b101, OPC_OP_IMM, "bexti">,
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} // Predicates = [HasStdExtZbs]
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let Predicates = [HasStdExtZbp] in {
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def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
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def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
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def GREVI : RVBShift_ri<0b01101, 0b101, OPC_OP_IMM, "grevi">, Sched<[]>;
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def GORCI : RVBShift_ri<0b00101, 0b101, OPC_OP_IMM, "gorci">, Sched<[]>;
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def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
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def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
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def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
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def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
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def XPERM_H : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
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def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
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def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
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def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
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def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
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def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
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def XPERM_W : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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// These instructions were named xperm.n and xperm.b in the last version of
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// the draft bit manipulation specification they were included in. However, we
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// use the mnemonics given to them in the ratified Zbkx extension.
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let Predicates = [HasStdExtZbpOrZbkx] in {
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def XPERM4 : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
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def XPERM8 : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
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} // Predicates = [HasStdExtZbpOrZbkx]
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let Predicates = [HasStdExtZbt] in {
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def CMIX : RVBTernaryR<0b11, 0b001, OPC_OP, "cmix", "$rd, $rs2, $rs1, $rs3">,
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Sched<[]>;
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@ -406,6 +441,15 @@ def FSRI : RVBTernaryImm6<0b101, OPC_OP_IMM, "fsri",
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"$rd, $rs1, $rs3, $shamt">, Sched<[]>;
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} // Predicates = [HasStdExtZbt]
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let Predicates = [HasStdExtZbt, IsRV64] in {
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def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32,
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"fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
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def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
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"$rd, $rs1, $rs3, $rs2">, Sched<[]>;
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def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
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"fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
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} // Predicates = [HasStdExtZbt, IsRV64]
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let Predicates = [HasStdExtZbb] in {
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def CLZ : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM, "clz">,
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Sched<[WriteCLZ, ReadCLZ]>;
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@ -415,9 +459,14 @@ def CPOP : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM, "cpop">,
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Sched<[WriteCPOP, ReadCPOP]>;
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} // Predicates = [HasStdExtZbb]
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let Predicates = [HasStdExtZbm, IsRV64] in
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def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, OPC_OP_IMM, "bmatflip">,
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Sched<[]>;
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let Predicates = [HasStdExtZbb, IsRV64] in {
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def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM_32, "clzw">,
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Sched<[WriteCLZ32, ReadCLZ32]>;
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def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM_32, "ctzw">,
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Sched<[WriteCTZ32, ReadCTZ32]>;
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def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM_32, "cpopw">,
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Sched<[WriteCPOP32, ReadCPOP32]>;
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} // Predicates = [HasStdExtZbb, IsRV64]
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let Predicates = [HasStdExtZbb] in {
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def SEXT_B : RVBUnary<0b0110000, 0b00100, 0b001, OPC_OP_IMM, "sext.b">,
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@ -433,13 +482,7 @@ def CRC32_H : RVBUnary<0b0110000, 0b10001, 0b001, OPC_OP_IMM, "crc32.h">,
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Sched<[]>;
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def CRC32_W : RVBUnary<0b0110000, 0b10010, 0b001, OPC_OP_IMM, "crc32.w">,
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Sched<[]>;
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} // Predicates = [HasStdExtZbr]
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let Predicates = [HasStdExtZbr, IsRV64] in
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def CRC32_D : RVBUnary<0b0110000, 0b10011, 0b001, OPC_OP_IMM, "crc32.d">,
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Sched<[]>;
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let Predicates = [HasStdExtZbr] in {
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def CRC32C_B : RVBUnary<0b0110000, 0b11000, 0b001, OPC_OP_IMM, "crc32c.b">,
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Sched<[]>;
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def CRC32C_H : RVBUnary<0b0110000, 0b11001, 0b001, OPC_OP_IMM, "crc32c.h">,
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@ -448,9 +491,13 @@ def CRC32C_W : RVBUnary<0b0110000, 0b11010, 0b001, OPC_OP_IMM, "crc32c.w">,
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Sched<[]>;
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} // Predicates = [HasStdExtZbr]
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let Predicates = [HasStdExtZbr, IsRV64] in
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let Predicates = [HasStdExtZbr, IsRV64] in {
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def CRC32_D : RVBUnary<0b0110000, 0b10011, 0b001, OPC_OP_IMM, "crc32.d">,
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Sched<[]>;
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def CRC32C_D : RVBUnary<0b0110000, 0b11011, 0b001, OPC_OP_IMM, "crc32c.d">,
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Sched<[]>;
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} // Predicates = [HasStdExtZbr, IsRV64]
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let Predicates = [HasStdExtZbc] in {
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def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr">,
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@ -476,8 +523,6 @@ def MAXU : ALU_rr<0b0000101, 0b111, "maxu">,
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} // Predicates = [HasStdExtZbb]
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let Predicates = [HasStdExtZbp] in {
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def SHFL : ALU_rr<0b0000100, 0b001, "shfl">, Sched<[]>;
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def UNSHFL : ALU_rr<0b0000100, 0b101, "unshfl">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZbe] in {
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@ -487,89 +532,6 @@ def BDECOMPRESS : ALU_rr<0b0100100, 0b110, "bdecompress">, Sched<[]>;
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def BCOMPRESS : ALU_rr<0b0000100, 0b110, "bcompress">, Sched<[]>;
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} // Predicates = [HasStdExtZbe]
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let Predicates = [HasStdExtZbpOrZbkb] in {
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def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
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def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
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} // Predicates = [HasStdExtZbpOrZbkb]
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let Predicates = [HasStdExtZbp] in
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def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
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let Predicates = [HasStdExtZbm, IsRV64] in {
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def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
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def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
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} // Predicates = [HasStdExtZbm, IsRV64]
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let Predicates = [HasStdExtZbf] in
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def BFP : ALU_rr<0b0100100, 0b111, "bfp">,
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Sched<[WriteBFP, ReadBFP, ReadBFP]>;
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let Predicates = [HasStdExtZbp] in {
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def SHFLI : RVBShfl_ri<0b0000100, 0b001, OPC_OP_IMM, "shfli">, Sched<[]>;
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def UNSHFLI : RVBShfl_ri<0b0000100, 0b101, OPC_OP_IMM, "unshfli">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZba, IsRV64] in {
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def SLLI_UW : RVBShift_ri<0b00001, 0b001, OPC_OP_IMM_32, "slli.uw">,
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Sched<[WriteShiftImm32, ReadShiftImm32]>;
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def ADD_UW : ALUW_rr<0b0000100, 0b000, "add.uw">,
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Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
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def SH1ADD_UW : ALUW_rr<0b0010000, 0b010, "sh1add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SH2ADD_UW : ALUW_rr<0b0010000, 0b100, "sh2add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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def SH3ADD_UW : ALUW_rr<0b0010000, 0b110, "sh3add.uw">,
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Sched<[WriteSHXADD32, ReadSHXADD32, ReadSHXADD32]>;
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} // Predicates = [HasStdExtZbb, IsRV64]
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
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def ROLW : ALUW_rr<0b0110000, 0b001, "rolw">,
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Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
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def RORW : ALUW_rr<0b0110000, 0b101, "rorw">,
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Sched<[WriteRotateReg32, ReadRotateReg32, ReadRotateReg32]>;
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} // Predicates = [HasStdExtZbbOrZbp, IsRV64]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">, Sched<[]>;
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def GREVW : ALUW_rr<0b0110100, 0b101, "grevw">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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def XPERM_W : ALU_rr<0b0010100, 0b000, "xperm.w">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in
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def RORIW : RVBShiftW_ri<0b0110000, 0b101, OPC_OP_IMM_32, "roriw">,
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Sched<[WriteRotateImm32, ReadRotateImm32]>;
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let Predicates = [HasStdExtZbp, IsRV64] in {
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def GORCIW : RVBShiftW_ri<0b0010100, 0b101, OPC_OP_IMM_32, "gorciw">, Sched<[]>;
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def GREVIW : RVBShiftW_ri<0b0110100, 0b101, OPC_OP_IMM_32, "greviw">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZbt, IsRV64] in {
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def FSLW : RVBTernaryR<0b10, 0b001, OPC_OP_32,
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"fslw", "$rd, $rs1, $rs3, $rs2">, Sched<[]>;
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def FSRW : RVBTernaryR<0b10, 0b101, OPC_OP_32, "fsrw",
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"$rd, $rs1, $rs3, $rs2">, Sched<[]>;
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def FSRIW : RVBTernaryImm5<0b10, 0b101, OPC_OP_IMM_32,
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"fsriw", "$rd, $rs1, $rs3, $shamt">, Sched<[]>;
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} // Predicates = [HasStdExtZbt, IsRV64]
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let Predicates = [HasStdExtZbb, IsRV64] in {
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def CLZW : RVBUnary<0b0110000, 0b00000, 0b001, OPC_OP_IMM_32, "clzw">,
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Sched<[WriteCLZ32, ReadCLZ32]>;
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def CTZW : RVBUnary<0b0110000, 0b00001, 0b001, OPC_OP_IMM_32, "ctzw">,
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Sched<[WriteCTZ32, ReadCTZ32]>;
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def CPOPW : RVBUnary<0b0110000, 0b00010, 0b001, OPC_OP_IMM_32, "cpopw">,
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Sched<[WriteCPOP32, ReadCPOP32]>;
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} // Predicates = [HasStdExtZbb, IsRV64]
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let Predicates = [HasStdExtZbp, IsRV64] in {
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def SHFLW : ALUW_rr<0b0000100, 0b001, "shflw">, Sched<[]>;
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def UNSHFLW : ALUW_rr<0b0000100, 0b101, "unshflw">, Sched<[]>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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let Predicates = [HasStdExtZbe, IsRV64] in {
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// NOTE: These mnemonics are from the 0.94 spec. There is a name conflict with
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// bextw in the 0.93 spec.
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@ -577,12 +539,32 @@ def BDECOMPRESSW : ALUW_rr<0b0100100, 0b110, "bdecompressw">, Sched<[]>;
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def BCOMPRESSW : ALUW_rr<0b0000100, 0b110, "bcompressw">, Sched<[]>;
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} // Predicates = [HasStdExtZbe, IsRV64]
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let Predicates = [HasStdExtZbpOrZbkb] in {
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def PACK : ALU_rr<0b0000100, 0b100, "pack">, Sched<[]>;
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def PACKH : ALU_rr<0b0000100, 0b111, "packh">, Sched<[]>;
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} // Predicates = [HasStdExtZbpOrZbkb]
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let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in
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def PACKW : ALUW_rr<0b0000100, 0b100, "packw">, Sched<[]>;
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let Predicates = [HasStdExtZbp] in
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def PACKU : ALU_rr<0b0100100, 0b100, "packu">, Sched<[]>;
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||||
|
||||
let Predicates = [HasStdExtZbp, IsRV64] in
|
||||
def PACKUW : ALUW_rr<0b0100100, 0b100, "packuw">, Sched<[]>;
|
||||
|
||||
let Predicates = [HasStdExtZbm, IsRV64] in {
|
||||
def BMATFLIP : RVBUnary<0b0110000, 0b00011, 0b001, OPC_OP_IMM, "bmatflip">,
|
||||
Sched<[]>;
|
||||
|
||||
def BMATOR : ALU_rr<0b0000100, 0b011, "bmator">, Sched<[]>;
|
||||
def BMATXOR : ALU_rr<0b0100100, 0b011, "bmatxor">, Sched<[]>;
|
||||
} // Predicates = [HasStdExtZbm, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbf] in
|
||||
def BFP : ALU_rr<0b0100100, 0b111, "bfp">,
|
||||
Sched<[WriteBFP, ReadBFP, ReadBFP]>;
|
||||
|
||||
let Predicates = [HasStdExtZbf, IsRV64] in
|
||||
def BFPW : ALUW_rr<0b0100100, 0b111, "bfpw">,
|
||||
Sched<[WriteBFP32, ReadBFP32, ReadBFP32]>;
|
||||
|
|
@ -771,8 +753,10 @@ def : InstAlias<"gorcw $rd, $rs1, $shamt",
|
|||
// Zbp is unratified and that it would likely adopt the already ratified Zbkx names.
|
||||
// Thus current Zbp instructions are defined as aliases for Zbkx instructions.
|
||||
let Predicates = [HasStdExtZbp] in {
|
||||
def : InstAlias<"xperm.b $rd, $rs1, $rs2", (XPERM8 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
|
||||
def : InstAlias<"xperm.n $rd, $rs1, $rs2", (XPERM4 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
|
||||
def : InstAlias<"xperm.b $rd, $rs1, $rs2",
|
||||
(XPERM8 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
|
||||
def : InstAlias<"xperm.n $rd, $rs1, $rs2",
|
||||
(XPERM4 GPR:$rd, GPR:$rs1, GPR:$rs2)>;
|
||||
} // Predicates = [HasStdExtZbp]
|
||||
|
||||
let Predicates = [HasStdExtZbs] in {
|
||||
|
|
@ -799,8 +783,22 @@ def : Pat<(xor GPR:$rs1, (not GPR:$rs2)), (XNOR GPR:$rs1, GPR:$rs2)>;
|
|||
let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
|
||||
def : PatGprGpr<rotl, ROL>;
|
||||
def : PatGprGpr<rotr, ROR>;
|
||||
|
||||
def : PatGprImm<rotr, RORI, uimmlog2xlen>;
|
||||
// There's no encoding for roli in the the 'B' extension as it can be
|
||||
// implemented with rori by negating the immediate.
|
||||
def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
|
||||
(RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
|
||||
} // Predicates = [HasStdExtZbbOrZbpOrZbkb]
|
||||
|
||||
let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
|
||||
def : PatGprGpr<riscv_rolw, ROLW>;
|
||||
def : PatGprGpr<riscv_rorw, RORW>;
|
||||
def : PatGprImm<riscv_rorw, RORIW, uimm5>;
|
||||
def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
|
||||
(RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
|
||||
} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbs] in {
|
||||
def : Pat<(and (not (shiftop<shl> 1, GPR:$rs2)), GPR:$rs1),
|
||||
(BCLR GPR:$rs1, GPR:$rs2)>;
|
||||
|
|
@ -848,14 +846,6 @@ def : Pat<(and GPR:$r, BCLRIANDIMask:$i),
|
|||
(BCLRITwoBitsMaskHigh BCLRIANDIMask:$i))>;
|
||||
}
|
||||
|
||||
// There's no encoding for roli in the the 'B' extension as it can be
|
||||
// implemented with rori by negating the immediate.
|
||||
let Predicates = [HasStdExtZbbOrZbpOrZbkb] in {
|
||||
def : PatGprImm<rotr, RORI, uimmlog2xlen>;
|
||||
def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
|
||||
(RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtZbbOrZbp] in {
|
||||
// We treat orc.b as a separate instruction, so match it directly. We also
|
||||
// lower the Zbb orc.b intrinsic to this.
|
||||
|
|
@ -865,24 +855,41 @@ def : Pat<(riscv_gorc GPR:$rs1, 7), (ORC_B GPR:$rs1)>;
|
|||
let Predicates = [HasStdExtZbp] in {
|
||||
def : PatGprGpr<riscv_grev, GREV>;
|
||||
def : PatGprGpr<riscv_gorc, GORC>;
|
||||
def : PatGprGpr<riscv_shfl, SHFL>;
|
||||
def : PatGprGpr<riscv_unshfl, UNSHFL>;
|
||||
def : PatGprGpr<int_riscv_xperm_n, XPERM4>;
|
||||
def : PatGprGpr<int_riscv_xperm_b, XPERM8>;
|
||||
def : PatGprGpr<int_riscv_xperm_h, XPERM_H>;
|
||||
def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>;
|
||||
def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
|
||||
def : PatGprImm<riscv_grev, GREVI, uimmlog2xlen>;
|
||||
def : PatGprImm<riscv_gorc, GORCI, uimmlog2xlen>;
|
||||
|
||||
// We treat brev8 as a separate instruction, so match it directly.
|
||||
def : Pat<(riscv_grev GPR:$rs1, 7), (BREV8 GPR:$rs1)>;
|
||||
|
||||
def : PatGprGpr<riscv_shfl, SHFL>;
|
||||
def : PatGprGpr<riscv_unshfl, UNSHFL>;
|
||||
def : PatGprImm<riscv_shfl, SHFLI, shfl_uimm>;
|
||||
def : PatGprImm<riscv_unshfl, UNSHFLI, shfl_uimm>;
|
||||
|
||||
def : PatGprGpr<int_riscv_xperm_n, XPERM4>;
|
||||
def : PatGprGpr<int_riscv_xperm_b, XPERM8>;
|
||||
def : PatGprGpr<int_riscv_xperm_h, XPERM_H>;
|
||||
} // Predicates = [HasStdExtZbp]
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV64] in {
|
||||
def : PatGprGpr<riscv_grevw, GREVW>;
|
||||
def : PatGprGpr<riscv_gorcw, GORCW>;
|
||||
def : PatGprImm<riscv_grevw, GREVIW, uimm5>;
|
||||
def : PatGprImm<riscv_gorcw, GORCIW, uimm5>;
|
||||
|
||||
// FIXME: Move to DAG combine.
|
||||
def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
|
||||
def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
|
||||
|
||||
def : PatGprGpr<riscv_shflw, SHFLW>;
|
||||
def : PatGprGpr<riscv_unshflw, UNSHFLW>;
|
||||
} // Predicates = [HasStdExtZbp, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV64] in
|
||||
def : PatGprGpr<int_riscv_xperm_w, XPERM_W>;
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV32] in {
|
||||
// FIXME : Move to DAG combine.
|
||||
def : Pat<(i32 (rotr (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
|
||||
def : Pat<(i32 (rotl (riscv_grev GPR:$rs1, 24), (i32 16))), (GREVI GPR:$rs1, 8)>;
|
||||
|
||||
|
|
@ -940,12 +947,31 @@ def : Pat<(riscv_fsl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
|
|||
(FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
|
||||
} // Predicates = [HasStdExtZbt]
|
||||
|
||||
let Predicates = [HasStdExtZbt, IsRV64] in {
|
||||
def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
|
||||
(FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
|
||||
def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, GPR:$rs2),
|
||||
(FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
|
||||
def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, uimm5:$shamt),
|
||||
(FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>;
|
||||
// We can use FSRIW for FSLW by immediate if we subtract the immediate from
|
||||
// 32 and swap the operands.
|
||||
def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
|
||||
(FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>;
|
||||
} // Predicates = [HasStdExtZbt, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbb] in {
|
||||
def : PatGpr<ctlz, CLZ>;
|
||||
def : PatGpr<cttz, CTZ>;
|
||||
def : PatGpr<ctpop, CPOP>;
|
||||
} // Predicates = [HasStdExtZbb]
|
||||
|
||||
let Predicates = [HasStdExtZbb, IsRV64] in {
|
||||
def : PatGpr<riscv_clzw, CLZW>;
|
||||
def : PatGpr<riscv_ctzw, CTZW>;
|
||||
def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;
|
||||
} // Predicates = [HasStdExtZbb, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbb] in {
|
||||
def : Pat<(sext_inreg GPR:$rs1, i8), (SEXT_B GPR:$rs1)>;
|
||||
def : Pat<(sext_inreg GPR:$rs1, i16), (SEXT_H GPR:$rs1)>;
|
||||
|
|
@ -966,22 +992,6 @@ let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
|
|||
def : Pat<(i64 (bswap GPR:$rs1)), (REV8_RV64 GPR:$rs1)>;
|
||||
} // Predicates = [HasStdExtZbbOrZbkb, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in
|
||||
def : Pat<(i32 (or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16)))),
|
||||
(PACK GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV32] in
|
||||
def : Pat<(i32 (or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16)))),
|
||||
(PACKU GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in
|
||||
def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))),
|
||||
(PACK GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV64] in
|
||||
def : Pat<(i64 (or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32)))),
|
||||
(PACKU GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
let Predicates = [HasStdExtZbpOrZbkb] in {
|
||||
def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
|
||||
(and GPR:$rs1, 0x00FF)),
|
||||
|
|
@ -991,6 +1001,36 @@ def : Pat<(or (shl (and GPR:$rs2, 0x00FF), (XLenVT 8)),
|
|||
(PACKH GPR:$rs1, GPR:$rs2)>;
|
||||
} // Predicates = [HasStdExtZbpOrZbkb]
|
||||
|
||||
let Predicates = [HasStdExtZbpOrZbkb, IsRV32] in
|
||||
def : Pat<(i32 (or (and GPR:$rs1, 0x0000FFFF), (shl GPR:$rs2, (i32 16)))),
|
||||
(PACK GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in {
|
||||
def : Pat<(i64 (or (and GPR:$rs1, 0x00000000FFFFFFFF), (shl GPR:$rs2, (i64 32)))),
|
||||
(PACK GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
|
||||
(and GPR:$rs1, 0x000000000000FFFF)),
|
||||
i32)),
|
||||
(PACKW GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
|
||||
(and GPR:$rs1, 0x000000000000FFFF))),
|
||||
(PACKW GPR:$rs1, GPR:$rs2)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV32] in
|
||||
def : Pat<(i32 (or (and GPR:$rs2, 0xFFFF0000), (srl GPR:$rs1, (i32 16)))),
|
||||
(PACKU GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV64] in {
|
||||
def : Pat<(i64 (or (and GPR:$rs2, 0xFFFFFFFF00000000), (srl GPR:$rs1, (i64 32)))),
|
||||
(PACKU GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
|
||||
(srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
|
||||
(PACKUW GPR:$rs1, GPR:$rs2)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtZbbOrZbp, IsRV32] in
|
||||
def : Pat<(i32 (and GPR:$rs, 0xFFFF)), (ZEXT_H_RV32 GPR:$rs)>;
|
||||
let Predicates = [HasStdExtZbbOrZbp, IsRV64] in
|
||||
|
|
@ -1092,60 +1132,6 @@ def : Pat<(i64 (add (and (shl GPR:$rs1, (i64 3)), 0x7FFFFFFFF), non_imm12:$rs2))
|
|||
(SH3ADD_UW GPR:$rs1, GPR:$rs2)>;
|
||||
} // Predicates = [HasStdExtZba, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64] in {
|
||||
def : PatGprGpr<riscv_rolw, ROLW>;
|
||||
def : PatGprGpr<riscv_rorw, RORW>;
|
||||
def : PatGprImm<riscv_rorw, RORIW, uimm5>;
|
||||
def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
|
||||
(RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
|
||||
} // Predicates = [HasStdExtZbbOrZbpOrZbkb, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV64] in {
|
||||
def : Pat<(riscv_rorw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
|
||||
def : Pat<(riscv_rolw (riscv_grevw GPR:$rs1, 24), 16), (GREVIW GPR:$rs1, 8)>;
|
||||
def : PatGprGpr<riscv_grevw, GREVW>;
|
||||
def : PatGprGpr<riscv_gorcw, GORCW>;
|
||||
def : PatGprGpr<riscv_shflw, SHFLW>;
|
||||
def : PatGprGpr<riscv_unshflw, UNSHFLW>;
|
||||
def : PatGprImm<riscv_grevw, GREVIW, uimm5>;
|
||||
def : PatGprImm<riscv_gorcw, GORCIW, uimm5>;
|
||||
} // Predicates = [HasStdExtZbp, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbt, IsRV64] in {
|
||||
def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
|
||||
(FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
|
||||
def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, GPR:$rs2),
|
||||
(FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
|
||||
def : Pat<(riscv_fsrw GPR:$rs1, GPR:$rs3, uimm5:$shamt),
|
||||
(FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>;
|
||||
// We can use FSRIW for FSLW by immediate if we subtract the immediate from
|
||||
// 32 and swap the operands.
|
||||
def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
|
||||
(FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>;
|
||||
} // Predicates = [HasStdExtZbt, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbb, IsRV64] in {
|
||||
def : PatGpr<riscv_clzw, CLZW>;
|
||||
def : PatGpr<riscv_ctzw, CTZW>;
|
||||
def : Pat<(i64 (ctpop (i64 (zexti32 (i64 GPR:$rs1))))), (CPOPW GPR:$rs1)>;
|
||||
} // Predicates = [HasStdExtZbb, IsRV64]
|
||||
|
||||
let Predicates = [HasStdExtZbpOrZbkb, IsRV64] in {
|
||||
def : Pat<(i64 (sext_inreg (or (shl GPR:$rs2, (i64 16)),
|
||||
(and GPR:$rs1, 0x000000000000FFFF)),
|
||||
i32)),
|
||||
(PACKW GPR:$rs1, GPR:$rs2)>;
|
||||
def : Pat<(i64 (or (sext_inreg (shl GPR:$rs2, (i64 16)), i32),
|
||||
(and GPR:$rs1, 0x000000000000FFFF))),
|
||||
(PACKW GPR:$rs1, GPR:$rs2)>;
|
||||
}
|
||||
|
||||
let Predicates = [HasStdExtZbp, IsRV64] in
|
||||
def : Pat<(i64 (or (and (assertsexti32 GPR:$rs2), 0xFFFFFFFFFFFF0000),
|
||||
(srl (and GPR:$rs1, 0xFFFFFFFF), (i64 16)))),
|
||||
(PACKUW GPR:$rs1, GPR:$rs2)>;
|
||||
|
||||
|
||||
let Predicates = [HasStdExtZbcOrZbkc] in {
|
||||
def : PatGprGpr<int_riscv_clmul, CLMUL>;
|
||||
def : PatGprGpr<int_riscv_clmulh, CLMULH>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue