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LegalizeTypes: Handle shift by 0 in ExpandShiftByConstant. 

Though such shifts are usually optimized away by combiner, we still can
encounter them after a vector shift is legalized.

llvm-svn: 231443
This commit is contained in:
Michael Zolotukhin 2015-03-06 01:13:01 +00:00
parent a5b9e1cf39
commit 03dd1082ad
2 changed files with 20 additions and 1 deletions
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9
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1333,12 +1333,19 @@ std::pair <SDValue, SDValue> DAGTypeLegalizer::ExpandAtomic(SDNode *Node) {
/// and the shift amount is a constant 'Amt'. Expand the operation.
void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt,
SDValue &Lo, SDValue &Hi) {
assert(Amt && "Expected zero shifts to be already optimized away.");
SDLoc DL(N);
// Expand the incoming operand to be shifted, so that we have its parts
SDValue InL, InH;
GetExpandedInteger(N->getOperand(0), InL, InH);
// Though Amt shouldn't usually be 0, it's possible. E.g. when legalization
// splitted a vector shift, like this: <op1, op2> SHL <0, 2>.
if (!Amt) {
Lo = InL;
Hi = InH;
return;
}
EVT NVT = InL.getValueType();
unsigned VTBits = N->getValueType(0).getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();

12
llvm/test/CodeGen/X86/vec_shift7.ll Normal file
View File

@ -0,0 +1,12 @@
; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
; Verify that we don't fail when shift by zero is encountered.
define i64 @test1(<2 x i64> %a) {
entry:
%c = shl <2 x i64> %a, <i64 0, i64 2>
%d = extractelement <2 x i64> %c, i32 0
ret i64 %d
}
; CHECK-LABEL: test1