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[MachineInstr] Teach the print method about RegisterBank. 

Properly print either the register class or the register bank or a
virtual register.
Get rid of a few ifdefs in the process.

llvm-svn: 265745
This commit is contained in:
Quentin Colombet 2016-04-07 23:18:11 +00:00
parent e217660591
commit 03c419628e
1 changed files with 10 additions and 11 deletions
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21
llvm/lib/CodeGen/MachineInstr.cpp
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@ -1689,12 +1689,9 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
unsigned Reg = getOperand(StartOp).getReg(); unsigned Reg = getOperand(StartOp).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) { if (TargetRegisterInfo::isVirtualRegister(Reg)) {
VirtRegs.push_back(Reg); VirtRegs.push_back(Reg);
#ifdef LLVM_BUILD_GLOBAL_ISEL
unsigned Size; unsigned Size;
if (MRI && (Size = MRI->getSize(Reg))) { if (MRI && (Size = MRI->getSize(Reg)))
OS << '(' << Size << ')'; OS << '(' << Size << ')';
}
#endif
} }
} }
@ -1873,16 +1870,18 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
HaveSemi = true; HaveSemi = true;
} }
for (unsigned i = 0; i != VirtRegs.size(); ++i) { for (unsigned i = 0; i != VirtRegs.size(); ++i) {
const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); const RegClassOrRegBank &RC = MRI->getRegClassOrRegBank(VirtRegs[i]);
#ifdef LLVM_BUILD_GLOBAL_ISEL
// Generic virtual registers do not have register classes.
if (!RC) if (!RC)
continue; continue;
#endif // Generic virtual registers do not have register classes.
OS << " " << TRI->getRegClassName(RC) if (RC.is<const RegisterBank *>())
<< ':' << PrintReg(VirtRegs[i]); OS << " " << RC.get<const RegisterBank *>()->getName();
else
OS << " "
<< TRI->getRegClassName(RC.get<const TargetRegisterClass *>());
OS << ':' << PrintReg(VirtRegs[i]);
for (unsigned j = i+1; j != VirtRegs.size();) { for (unsigned j = i+1; j != VirtRegs.size();) {
if (MRI->getRegClass(VirtRegs[j]) != RC) { if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) {
++j; ++j;
continue; continue;
} }