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AMDGPU: Fix warnings introduced by r310336 

llvm-svn: 310337
This commit is contained in:
Tom Stellard 2017-08-08 05:52:00 +00:00
parent 20287697f8
commit 03aa3aee11
1 changed files with 2 additions and 4 deletions
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6
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
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@ -383,7 +383,6 @@ static bool getConstantValue(SDValue N, uint32_t &Out) {
} }
void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
unsigned Opc = N->getOpcode();
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
unsigned NumVectorElts = VT.getVectorNumElements(); unsigned NumVectorElts = VT.getVectorNumElements();
EVT EltVT = VT.getVectorElementType(); EVT EltVT = VT.getVectorElementType();
@ -420,7 +419,7 @@ void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
} }
if (NOps != NumVectorElts) { if (NOps != NumVectorElts) {
// Fill in the missing undef elements if this was a scalar_to_vector. // Fill in the missing undef elements if this was a scalar_to_vector.
assert(Opc == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts); assert(N->getOpcode() == ISD::SCALAR_TO_VECTOR && NOps < NumVectorElts);
MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, MachineSDNode *ImpDef = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,
DL, EltVT); DL, EltVT);
for (unsigned i = NOps; i < NumVectorElts; ++i) { for (unsigned i = NOps; i < NumVectorElts; ++i) {
@ -481,7 +480,6 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
case ISD::BUILD_VECTOR: { case ISD::BUILD_VECTOR: {
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
unsigned NumVectorElts = VT.getVectorNumElements(); unsigned NumVectorElts = VT.getVectorNumElements();
EVT EltVT = VT.getVectorElementType();
if (VT == MVT::v2i16 || VT == MVT::v2f16) { if (VT == MVT::v2i16 || VT == MVT::v2f16) {
if (Opc == ISD::BUILD_VECTOR) { if (Opc == ISD::BUILD_VECTOR) {
@ -498,7 +496,7 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
break; break;
} }
assert(EltVT.bitsEq(MVT::i32)); assert(VT.getVectorElementType().bitsEq(MVT::i32));
unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts); unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
SelectBuildVector(N, RegClassID); SelectBuildVector(N, RegClassID);
return; return;