forked from OSchip/llvm-project
[PowerPC] Implement probing for dynamic stack allocation
This patch is part of supporting `-fstack-clash-protection`. Mainly do such things compared to existing `lowerDynamicAlloc` - Added a new pseudo instruction PPC::PREPARE_PROBED_ALLOC to get actual frame pointer and final stack pointer. - Synthesize a loop to probe by blocks. - Use DYNAREAOFFSET to get MaxCallFrameSize which is calculated in prologepilog. Differential Revision: https://reviews.llvm.org/D81358
This commit is contained in:
Kai Luo
parent
52855ed099
commit
03828e38c3
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@ -126,6 +126,7 @@ cl::desc("use absolute jump tables on ppc"), cl::Hidden);
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STATISTIC(NumTailCalls, "Number of tail calls");
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STATISTIC(NumSiblingCalls, "Number of sibling calls");
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STATISTIC(ShufflesHandledWithVPERM, "Number of shuffles lowered to a VPERM");
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STATISTIC(NumDynamicAllocaProbed, "Number of dynamic stack allocation probed");
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static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
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@ -1486,6 +1487,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case PPCISD::ATOMIC_CMP_SWAP_16: return "PPCISD::ATOMIC_CMP_SWAP_16";
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case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
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case PPCISD::DYNAREAOFFSET: return "PPCISD::DYNAREAOFFSET";
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case PPCISD::PROBED_ALLOCA: return "PPCISD::PROBED_ALLOCA";
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case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
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case PPCISD::SRL: return "PPCISD::SRL";
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case PPCISD::SRA: return "PPCISD::SRA";
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@ -7919,6 +7921,7 @@ PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
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SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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SelectionDAG &DAG) const {
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MachineFunction &MF = DAG.getMachineFunction();
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// Get the inputs.
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SDValue Chain = Op.getOperand(0);
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SDValue Size = Op.getOperand(1);
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@ -7931,9 +7934,10 @@ SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
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DAG.getConstant(0, dl, PtrVT), Size);
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// Construct a node for the frame pointer save index.
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SDValue FPSIdx = getFramePointerFrameIndex(DAG);
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// Build a DYNALLOC node.
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SDValue Ops[3] = { Chain, NegSize, FPSIdx };
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SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
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if (hasInlineStackProbe(MF))
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return DAG.getNode(PPCISD::PROBED_ALLOCA, dl, VTs, Ops);
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return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
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}
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@ -11799,6 +11803,184 @@ PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr &MI,
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return MBB;
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}
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bool PPCTargetLowering::hasInlineStackProbe(MachineFunction &MF) const {
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// If the function specifically requests inline stack probes, emit them.
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if (MF.getFunction().hasFnAttribute("probe-stack"))
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return MF.getFunction().getFnAttribute("probe-stack").getValueAsString() ==
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"inline-asm";
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return false;
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}
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unsigned PPCTargetLowering::getStackProbeSize(MachineFunction &MF) const {
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const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
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unsigned StackAlign = TFI->getStackAlignment();
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assert(StackAlign >= 1 && isPowerOf2_32(StackAlign) &&
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"Unexpected stack alignment");
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// The default stack probe size is 4096 if the function has no
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// stack-probe-size attribute.
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unsigned StackProbeSize = 4096;
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const Function &Fn = MF.getFunction();
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if (Fn.hasFnAttribute("stack-probe-size"))
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Fn.getFnAttribute("stack-probe-size")
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.getValueAsString()
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.getAsInteger(0, StackProbeSize);
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// Round down to the stack alignment.
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StackProbeSize &= ~(StackAlign - 1);
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return StackProbeSize ? StackProbeSize : StackAlign;
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}
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// Lower dynamic stack allocation with probing. `emitProbedAlloca` is splitted
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// into three phases. In the first phase, it uses pseudo instruction
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// PREPARE_PROBED_ALLOCA to get the future result of actual FramePointer and
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// FinalStackPtr. In the second phase, it generates a loop for probing blocks.
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// At last, it uses pseudo instruction DYNAREAOFFSET to get the future result of
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// MaxCallFrameSize so that it can calculate correct data area pointer.
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MachineBasicBlock *
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PPCTargetLowering::emitProbedAlloca(MachineInstr &MI,
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MachineBasicBlock *MBB) const {
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const bool isPPC64 = Subtarget.isPPC64();
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MachineFunction *MF = MBB->getParent();
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const TargetInstrInfo *TII = Subtarget.getInstrInfo();
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DebugLoc DL = MI.getDebugLoc();
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const unsigned ProbeSize = getStackProbeSize(*MF);
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const BasicBlock *ProbedBB = MBB->getBasicBlock();
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MachineRegisterInfo &MRI = MF->getRegInfo();
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// The CFG of probing stack looks as
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// +-----+
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// | MBB |
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// +--+--+
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// |
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// +----v----+
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// +--->+ TestMBB +---+
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// | +----+----+ |
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// | | |
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// | +-----v----+ |
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// +---+ BlockMBB | |
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// +----------+ |
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// |
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// +---------+ |
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// | TailMBB +<--+
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// +---------+
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// In MBB, calculate previous frame pointer and final stack pointer.
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// In TestMBB, test if sp is equal to final stack pointer, if so, jump to
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// TailMBB. In BlockMBB, update the sp atomically and jump back to TestMBB.
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// TailMBB is spliced via \p MI.
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MachineBasicBlock *TestMBB = MF->CreateMachineBasicBlock(ProbedBB);
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MachineBasicBlock *TailMBB = MF->CreateMachineBasicBlock(ProbedBB);
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MachineBasicBlock *BlockMBB = MF->CreateMachineBasicBlock(ProbedBB);
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MachineFunction::iterator MBBIter = ++MBB->getIterator();
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MF->insert(MBBIter, TestMBB);
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MF->insert(MBBIter, BlockMBB);
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MF->insert(MBBIter, TailMBB);
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const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
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const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
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Register DstReg = MI.getOperand(0).getReg();
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Register NegSizeReg = MI.getOperand(1).getReg();
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Register SPReg = isPPC64 ? PPC::X1 : PPC::R1;
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Register FinalStackPtr = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
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Register FramePointer = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
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// Get the canonical FinalStackPtr like what
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// PPCRegisterInfo::lowerDynamicAlloc does.
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BuildMI(*MBB, {MI}, DL,
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TII->get(isPPC64 ? PPC::PREPARE_PROBED_ALLOCA_64
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: PPC::PREPARE_PROBED_ALLOCA_32),
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FramePointer)
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.addDef(FinalStackPtr)
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.addReg(NegSizeReg)
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.add(MI.getOperand(2))
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.add(MI.getOperand(3));
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// Materialize a scratch register for update.
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int64_t NegProbeSize = -(int64_t)ProbeSize;
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assert(isInt<32>(NegProbeSize) && "Unhandled probe size!");
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Register ScratchReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
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if (!isInt<16>(NegProbeSize)) {
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Register TempReg = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
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BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LIS8 : PPC::LIS), TempReg)
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.addImm(NegProbeSize >> 16);
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BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::ORI8 : PPC::ORI),
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ScratchReg)
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.addReg(TempReg)
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.addImm(NegProbeSize & 0xFFFF);
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} else
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BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::LI8 : PPC::LI), ScratchReg)
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.addImm(NegProbeSize);
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{
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// Probing leading residual part.
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Register Div = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
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BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::DIVD : PPC::DIVW), Div)
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.addReg(NegSizeReg)
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.addReg(ScratchReg);
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Register Mul = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
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BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::MULLD : PPC::MULLW), Mul)
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.addReg(Div)
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.addReg(ScratchReg);
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Register NegMod = MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
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BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::SUBF8 : PPC::SUBF), NegMod)
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.addReg(Mul)
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.addReg(NegSizeReg);
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BuildMI(*MBB, {MI}, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
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.addReg(FramePointer)
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.addReg(SPReg)
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.addReg(NegMod);
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}
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{
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// Remaining part should be multiple of ProbeSize.
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Register CmpResult = MRI.createVirtualRegister(&PPC::CRRCRegClass);
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BuildMI(TestMBB, DL, TII->get(isPPC64 ? PPC::CMPD : PPC::CMPW), CmpResult)
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.addReg(SPReg)
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.addReg(FinalStackPtr);
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BuildMI(TestMBB, DL, TII->get(PPC::BCC))
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.addImm(PPC::PRED_EQ)
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.addReg(CmpResult)
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.addMBB(TailMBB);
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TestMBB->addSuccessor(BlockMBB);
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TestMBB->addSuccessor(TailMBB);
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}
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{
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// Touch the block.
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// |P...|P...|P...
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BuildMI(BlockMBB, DL, TII->get(isPPC64 ? PPC::STDUX : PPC::STWUX), SPReg)
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.addReg(FramePointer)
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.addReg(SPReg)
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.addReg(ScratchReg);
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BuildMI(BlockMBB, DL, TII->get(PPC::B)).addMBB(TestMBB);
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BlockMBB->addSuccessor(TestMBB);
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}
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// Calculation of MaxCallFrameSize is deferred to prologepilog, use
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// DYNAREAOFFSET pseudo instruction to get the future result.
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Register MaxCallFrameSizeReg =
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MRI.createVirtualRegister(isPPC64 ? G8RC : GPRC);
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BuildMI(TailMBB, DL,
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TII->get(isPPC64 ? PPC::DYNAREAOFFSET8 : PPC::DYNAREAOFFSET),
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MaxCallFrameSizeReg)
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.add(MI.getOperand(2))
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.add(MI.getOperand(3));
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BuildMI(TailMBB, DL, TII->get(isPPC64 ? PPC::ADD8 : PPC::ADD4), DstReg)
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.addReg(SPReg)
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.addReg(MaxCallFrameSizeReg);
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// Splice instructions after MI to TailMBB.
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TailMBB->splice(TailMBB->end(), MBB,
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std::next(MachineBasicBlock::iterator(MI)), MBB->end());
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TailMBB->transferSuccessorsAndUpdatePHIs(MBB);
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MBB->addSuccessor(TestMBB);
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// Delete the pseudo instruction.
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MI.eraseFromParent();
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++NumDynamicAllocaProbed;
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return TailMBB;
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}
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MachineBasicBlock *
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PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *BB) const {
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@ -12565,6 +12747,9 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
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.addReg(NewFPSCRReg)
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.addImm(0)
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.addImm(0);
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} else if (MI.getOpcode() == PPC::PROBED_ALLOCA_32 ||
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MI.getOpcode() == PPC::PROBED_ALLOCA_64) {
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return emitProbedAlloca(MI, BB);
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} else {
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llvm_unreachable("Unexpected instr type to insert");
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}
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@ -138,6 +138,10 @@ namespace llvm {
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/// dynamic alloca.
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DYNAREAOFFSET,
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/// To avoid stack clash, allocation is performed by block and each block is
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/// probed.
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PROBED_ALLOCA,
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/// GlobalBaseReg - On Darwin, this node represents the result of the mflr
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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@ -804,6 +808,13 @@ namespace llvm {
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MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr &MI,
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MachineBasicBlock *MBB) const;
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MachineBasicBlock *emitProbedAlloca(MachineInstr &MI,
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MachineBasicBlock *MBB) const;
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bool hasInlineStackProbe(MachineFunction &MF) const override;
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unsigned getStackProbeSize(MachineFunction &MF) const;
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ConstraintType getConstraintType(StringRef Constraint) const override;
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/// Examine constraint string and operand type and determine a weight value.
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@ -425,6 +425,16 @@ def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri
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(PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
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def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8",
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[(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
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// Probed alloca to support stack clash protection.
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let Defs = [X1], Uses = [X1], hasNoSchedulingInfo = 1 in {
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def PROBED_ALLOCA_64 : PPCCustomInserterPseudo<(outs g8rc:$result),
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(ins g8rc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_64",
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[(set i64:$result,
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(PPCprobedalloca i64:$negsize, iaddr:$fpsi))]>;
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def PREPARE_PROBED_ALLOCA_64 : PPCEmitTimePseudo<(outs g8rc:$fp,
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g8rc:$sp),
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(ins g8rc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_64", []>;
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}
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let hasSideEffects = 0 in {
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let Defs = [LR8] in {
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@ -323,6 +323,7 @@ def SDTDynOp : SDTypeProfile<1, 2, []>;
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def SDTDynAreaOp : SDTypeProfile<1, 1, []>;
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def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
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def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
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def PPCprobedalloca : SDNode<"PPCISD::PROBED_ALLOCA", SDTDynOp, [SDNPHasChain]>;
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// PC Relative Specific Nodes
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def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>;
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@ -1399,6 +1400,16 @@ def DYNALLOC : PPCEmitTimePseudo<(outs gprc:$result), (ins gprc:$negsize, memri:
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(PPCdynalloc i32:$negsize, iaddr:$fpsi))]>;
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def DYNAREAOFFSET : PPCEmitTimePseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
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[(set i32:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
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// Probed alloca to support stack clash protection.
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let Defs = [R1], Uses = [R1], hasNoSchedulingInfo = 1 in {
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def PROBED_ALLOCA_32 : PPCCustomInserterPseudo<(outs gprc:$result),
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(ins gprc:$negsize, memri:$fpsi), "#PROBED_ALLOCA_32",
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[(set i32:$result,
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(PPCprobedalloca i32:$negsize, iaddr:$fpsi))]>;
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def PREPARE_PROBED_ALLOCA_32 : PPCEmitTimePseudo<(outs gprc:$fp,
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gprc:$sp),
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(ins gprc:$negsize, memri:$fpsi), "#PREPARE_PROBED_ALLOCA_32", []>;
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}
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// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
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// instruction selection into a branch sequence.
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@ -610,6 +610,38 @@ void PPCRegisterInfo::prepareDynamicAlloca(MachineBasicBlock::iterator II,
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}
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}
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void PPCRegisterInfo::lowerPrepareProbedAlloca(
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MachineBasicBlock::iterator II) const {
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MachineInstr &MI = *II;
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// Get the instruction's basic block.
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MachineBasicBlock &MBB = *MI.getParent();
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// Get the basic block's function.
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MachineFunction &MF = *MBB.getParent();
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const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
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// Get the instruction info.
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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// Determine whether 64-bit pointers are used.
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bool LP64 = TM.isPPC64();
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DebugLoc dl = MI.getDebugLoc();
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Register FramePointer = MI.getOperand(0).getReg();
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Register FinalStackPtr = MI.getOperand(1).getReg();
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bool KillNegSizeReg = MI.getOperand(2).isKill();
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Register NegSizeReg = MI.getOperand(2).getReg();
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prepareDynamicAlloca(II, NegSizeReg, KillNegSizeReg, FramePointer);
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if (LP64) {
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BuildMI(MBB, II, dl, TII.get(PPC::ADD8), FinalStackPtr)
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.addReg(PPC::X1)
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.addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
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} else {
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BuildMI(MBB, II, dl, TII.get(PPC::ADD4), FinalStackPtr)
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.addReg(PPC::R1)
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.addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
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}
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MBB.erase(II);
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}
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void PPCRegisterInfo::lowerDynamicAreaOffset(
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MachineBasicBlock::iterator II) const {
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// Get the instruction.
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@ -1050,6 +1082,13 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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return;
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}
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if (FPSI && FrameIndex == FPSI &&
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(OpC == PPC::PREPARE_PROBED_ALLOCA_64 ||
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OpC == PPC::PREPARE_PROBED_ALLOCA_32)) {
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lowerPrepareProbedAlloca(II);
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return;
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}
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// Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc.
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if (OpC == PPC::SPILL_CR) {
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lowerCRSpilling(II, FrameIndex);
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@ -110,6 +110,7 @@ public:
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void prepareDynamicAlloca(MachineBasicBlock::iterator II,
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Register &NegSizeReg, bool &KillNegSizeReg,
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Register &FramePointer) const;
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void lowerPrepareProbedAlloca(MachineBasicBlock::iterator II) const;
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void lowerCRSpilling(MachineBasicBlock::iterator II,
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unsigned FrameIndex) const;
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void lowerCRRestore(MachineBasicBlock::iterator II,
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@ -0,0 +1,437 @@
|
|||
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||||
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
|
||||
; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
|
||||
; RUN: -check-prefix=CHECK-LE %s
|
||||
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
|
||||
; RUN: -mtriple=powerpc64le-linux-gnu -mcpu=pwr9 < %s | FileCheck \
|
||||
; RUN: -check-prefix=CHECK-P9-LE %s
|
||||
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
|
||||
; RUN: -mtriple=powerpc64-linux-gnu < %s | FileCheck \
|
||||
; RUN: -check-prefix=CHECK-BE %s
|
||||
; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
|
||||
; RUN: -mtriple=powerpc-linux-gnu < %s | FileCheck \
|
||||
; RUN: -check-prefix=CHECK-32 %s
|
||||
|
||||
define i32 @foo(i32 %n) local_unnamed_addr #0 "stack-probe-size"="32768" nounwind {
|
||||
; CHECK-LE-LABEL: foo:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: std r31, -8(r1)
|
||||
; CHECK-LE-NEXT: stdu r1, -48(r1)
|
||||
; CHECK-LE-NEXT: rldic r3, r3, 2, 30
|
||||
; CHECK-LE-NEXT: li r6, -32768
|
||||
; CHECK-LE-NEXT: mr r31, r1
|
||||
; CHECK-LE-NEXT: addi r3, r3, 15
|
||||
; CHECK-LE-NEXT: addi r4, r31, 48
|
||||
; CHECK-LE-NEXT: rldicl r3, r3, 60, 4
|
||||
; CHECK-LE-NEXT: rldicl r3, r3, 4, 29
|
||||
; CHECK-LE-NEXT: neg r5, r3
|
||||
; CHECK-LE-NEXT: divd r7, r5, r6
|
||||
; CHECK-LE-NEXT: add r3, r1, r5
|
||||
; CHECK-LE-NEXT: mulld r6, r7, r6
|
||||
; CHECK-LE-NEXT: sub r5, r5, r6
|
||||
; CHECK-LE-NEXT: stdux r4, r1, r5
|
||||
; CHECK-LE-NEXT: cmpd r1, r3
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB0_2
|
||||
; CHECK-LE-NEXT: .LBB0_1:
|
||||
; CHECK-LE-NEXT: stdu r4, -32768(r1)
|
||||
; CHECK-LE-NEXT: cmpd r1, r3
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB0_1
|
||||
; CHECK-LE-NEXT: .LBB0_2:
|
||||
; CHECK-LE-NEXT: li r4, 1
|
||||
; CHECK-LE-NEXT: addi r3, r1, 32
|
||||
; CHECK-LE-NEXT: stw r4, 4792(r3)
|
||||
; CHECK-LE-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-LE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LE-LABEL: foo:
|
||||
; CHECK-P9-LE: # %bb.0:
|
||||
; CHECK-P9-LE-NEXT: std r31, -8(r1)
|
||||
; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
|
||||
; CHECK-P9-LE-NEXT: rldic r3, r3, 2, 30
|
||||
; CHECK-P9-LE-NEXT: addi r3, r3, 15
|
||||
; CHECK-P9-LE-NEXT: rldicl r3, r3, 60, 4
|
||||
; CHECK-P9-LE-NEXT: rldicl r3, r3, 4, 29
|
||||
; CHECK-P9-LE-NEXT: neg r5, r3
|
||||
; CHECK-P9-LE-NEXT: li r6, -32768
|
||||
; CHECK-P9-LE-NEXT: divd r7, r5, r6
|
||||
; CHECK-P9-LE-NEXT: mulld r6, r7, r6
|
||||
; CHECK-P9-LE-NEXT: mr r31, r1
|
||||
; CHECK-P9-LE-NEXT: addi r4, r31, 48
|
||||
; CHECK-P9-LE-NEXT: add r3, r1, r5
|
||||
; CHECK-P9-LE-NEXT: sub r5, r5, r6
|
||||
; CHECK-P9-LE-NEXT: stdux r4, r1, r5
|
||||
; CHECK-P9-LE-NEXT: cmpd r1, r3
|
||||
; CHECK-P9-LE-NEXT: beq cr0, .LBB0_2
|
||||
; CHECK-P9-LE-NEXT: .LBB0_1:
|
||||
; CHECK-P9-LE-NEXT: stdu r4, -32768(r1)
|
||||
; CHECK-P9-LE-NEXT: cmpd r1, r3
|
||||
; CHECK-P9-LE-NEXT: bne cr0, .LBB0_1
|
||||
; CHECK-P9-LE-NEXT: .LBB0_2:
|
||||
; CHECK-P9-LE-NEXT: addi r3, r1, 32
|
||||
; CHECK-P9-LE-NEXT: li r4, 1
|
||||
; CHECK-P9-LE-NEXT: stw r4, 4792(r3)
|
||||
; CHECK-P9-LE-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-P9-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-P9-LE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-P9-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: foo:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: std r31, -8(r1)
|
||||
; CHECK-BE-NEXT: stdu r1, -64(r1)
|
||||
; CHECK-BE-NEXT: rldic r3, r3, 2, 30
|
||||
; CHECK-BE-NEXT: li r6, -32768
|
||||
; CHECK-BE-NEXT: addi r3, r3, 15
|
||||
; CHECK-BE-NEXT: rldicl r3, r3, 60, 4
|
||||
; CHECK-BE-NEXT: mr r31, r1
|
||||
; CHECK-BE-NEXT: rldicl r3, r3, 4, 29
|
||||
; CHECK-BE-NEXT: addi r4, r31, 64
|
||||
; CHECK-BE-NEXT: neg r5, r3
|
||||
; CHECK-BE-NEXT: divd r7, r5, r6
|
||||
; CHECK-BE-NEXT: add r3, r1, r5
|
||||
; CHECK-BE-NEXT: mulld r6, r7, r6
|
||||
; CHECK-BE-NEXT: sub r5, r5, r6
|
||||
; CHECK-BE-NEXT: stdux r4, r1, r5
|
||||
; CHECK-BE-NEXT: cmpd r1, r3
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB0_2
|
||||
; CHECK-BE-NEXT: .LBB0_1:
|
||||
; CHECK-BE-NEXT: stdu r4, -32768(r1)
|
||||
; CHECK-BE-NEXT: cmpd r1, r3
|
||||
; CHECK-BE-NEXT: bne cr0, .LBB0_1
|
||||
; CHECK-BE-NEXT: .LBB0_2:
|
||||
; CHECK-BE-NEXT: li r4, 1
|
||||
; CHECK-BE-NEXT: addi r3, r1, 48
|
||||
; CHECK-BE-NEXT: stw r4, 4792(r3)
|
||||
; CHECK-BE-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-BE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-BE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
;
|
||||
; CHECK-32-LABEL: foo:
|
||||
; CHECK-32: # %bb.0:
|
||||
; CHECK-32-NEXT: stwu r1, -32(r1)
|
||||
; CHECK-32-NEXT: slwi r3, r3, 2
|
||||
; CHECK-32-NEXT: addi r3, r3, 15
|
||||
; CHECK-32-NEXT: rlwinm r3, r3, 0, 0, 27
|
||||
; CHECK-32-NEXT: neg r5, r3
|
||||
; CHECK-32-NEXT: li r6, -32768
|
||||
; CHECK-32-NEXT: divw r7, r5, r6
|
||||
; CHECK-32-NEXT: stw r31, 28(r1)
|
||||
; CHECK-32-NEXT: mr r31, r1
|
||||
; CHECK-32-NEXT: addi r4, r31, 32
|
||||
; CHECK-32-NEXT: add r3, r1, r5
|
||||
; CHECK-32-NEXT: mullw r6, r7, r6
|
||||
; CHECK-32-NEXT: sub r5, r5, r6
|
||||
; CHECK-32-NEXT: stwux r4, r1, r5
|
||||
; CHECK-32-NEXT: cmpw r1, r3
|
||||
; CHECK-32-NEXT: beq cr0, .LBB0_2
|
||||
; CHECK-32-NEXT: .LBB0_1:
|
||||
; CHECK-32-NEXT: stwu r4, -32768(r1)
|
||||
; CHECK-32-NEXT: cmpw r1, r3
|
||||
; CHECK-32-NEXT: bne cr0, .LBB0_1
|
||||
; CHECK-32-NEXT: .LBB0_2:
|
||||
; CHECK-32-NEXT: li r4, 1
|
||||
; CHECK-32-NEXT: addi r3, r1, 16
|
||||
; CHECK-32-NEXT: stw r4, 4792(r3)
|
||||
; CHECK-32-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-32-NEXT: lwz r31, 0(r1)
|
||||
; CHECK-32-NEXT: lwz r0, -4(r31)
|
||||
; CHECK-32-NEXT: mr r1, r31
|
||||
; CHECK-32-NEXT: mr r31, r0
|
||||
; CHECK-32-NEXT: blr
|
||||
%a = alloca i32, i32 %n, align 16
|
||||
%b = getelementptr inbounds i32, i32* %a, i64 1198
|
||||
store volatile i32 1, i32* %b
|
||||
%c = load volatile i32, i32* %a
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @bar(i32 %n) local_unnamed_addr #0 nounwind {
|
||||
; CHECK-LE-LABEL: bar:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: std r31, -8(r1)
|
||||
; CHECK-LE-NEXT: stdu r1, -48(r1)
|
||||
; CHECK-LE-NEXT: rldic r4, r3, 2, 30
|
||||
; CHECK-LE-NEXT: li r7, -4096
|
||||
; CHECK-LE-NEXT: mr r31, r1
|
||||
; CHECK-LE-NEXT: addi r4, r4, 15
|
||||
; CHECK-LE-NEXT: addi r5, r31, 48
|
||||
; CHECK-LE-NEXT: rldicl r4, r4, 60, 4
|
||||
; CHECK-LE-NEXT: rldicl r4, r4, 4, 29
|
||||
; CHECK-LE-NEXT: neg r6, r4
|
||||
; CHECK-LE-NEXT: divd r8, r6, r7
|
||||
; CHECK-LE-NEXT: add r4, r1, r6
|
||||
; CHECK-LE-NEXT: mulld r7, r8, r7
|
||||
; CHECK-LE-NEXT: sub r6, r6, r7
|
||||
; CHECK-LE-NEXT: stdux r5, r1, r6
|
||||
; CHECK-LE-NEXT: cmpd r1, r4
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB1_2
|
||||
; CHECK-LE-NEXT: .LBB1_1:
|
||||
; CHECK-LE-NEXT: stdu r5, -4096(r1)
|
||||
; CHECK-LE-NEXT: cmpd r1, r4
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB1_1
|
||||
; CHECK-LE-NEXT: .LBB1_2:
|
||||
; CHECK-LE-NEXT: extsw r3, r3
|
||||
; CHECK-LE-NEXT: li r5, 1
|
||||
; CHECK-LE-NEXT: addi r4, r1, 32
|
||||
; CHECK-LE-NEXT: sldi r3, r3, 2
|
||||
; CHECK-LE-NEXT: add r3, r4, r3
|
||||
; CHECK-LE-NEXT: stw r5, 4096(r3)
|
||||
; CHECK-LE-NEXT: lwz r3, 0(r4)
|
||||
; CHECK-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-LE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LE-LABEL: bar:
|
||||
; CHECK-P9-LE: # %bb.0:
|
||||
; CHECK-P9-LE-NEXT: std r31, -8(r1)
|
||||
; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
|
||||
; CHECK-P9-LE-NEXT: rldic r4, r3, 2, 30
|
||||
; CHECK-P9-LE-NEXT: addi r4, r4, 15
|
||||
; CHECK-P9-LE-NEXT: rldicl r4, r4, 60, 4
|
||||
; CHECK-P9-LE-NEXT: rldicl r4, r4, 4, 29
|
||||
; CHECK-P9-LE-NEXT: neg r6, r4
|
||||
; CHECK-P9-LE-NEXT: li r7, -4096
|
||||
; CHECK-P9-LE-NEXT: divd r8, r6, r7
|
||||
; CHECK-P9-LE-NEXT: mulld r7, r8, r7
|
||||
; CHECK-P9-LE-NEXT: mr r31, r1
|
||||
; CHECK-P9-LE-NEXT: addi r5, r31, 48
|
||||
; CHECK-P9-LE-NEXT: add r4, r1, r6
|
||||
; CHECK-P9-LE-NEXT: sub r6, r6, r7
|
||||
; CHECK-P9-LE-NEXT: stdux r5, r1, r6
|
||||
; CHECK-P9-LE-NEXT: cmpd r1, r4
|
||||
; CHECK-P9-LE-NEXT: beq cr0, .LBB1_2
|
||||
; CHECK-P9-LE-NEXT: .LBB1_1:
|
||||
; CHECK-P9-LE-NEXT: stdu r5, -4096(r1)
|
||||
; CHECK-P9-LE-NEXT: cmpd r1, r4
|
||||
; CHECK-P9-LE-NEXT: bne cr0, .LBB1_1
|
||||
; CHECK-P9-LE-NEXT: .LBB1_2:
|
||||
; CHECK-P9-LE-NEXT: addi r4, r1, 32
|
||||
; CHECK-P9-LE-NEXT: extswsli r3, r3, 2
|
||||
; CHECK-P9-LE-NEXT: add r3, r4, r3
|
||||
; CHECK-P9-LE-NEXT: li r5, 1
|
||||
; CHECK-P9-LE-NEXT: stw r5, 4096(r3)
|
||||
; CHECK-P9-LE-NEXT: lwz r3, 0(r4)
|
||||
; CHECK-P9-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-P9-LE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-P9-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: bar:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: std r31, -8(r1)
|
||||
; CHECK-BE-NEXT: stdu r1, -64(r1)
|
||||
; CHECK-BE-NEXT: rldic r4, r3, 2, 30
|
||||
; CHECK-BE-NEXT: li r7, -4096
|
||||
; CHECK-BE-NEXT: addi r4, r4, 15
|
||||
; CHECK-BE-NEXT: rldicl r4, r4, 60, 4
|
||||
; CHECK-BE-NEXT: mr r31, r1
|
||||
; CHECK-BE-NEXT: rldicl r4, r4, 4, 29
|
||||
; CHECK-BE-NEXT: addi r5, r31, 64
|
||||
; CHECK-BE-NEXT: neg r6, r4
|
||||
; CHECK-BE-NEXT: divd r8, r6, r7
|
||||
; CHECK-BE-NEXT: add r4, r1, r6
|
||||
; CHECK-BE-NEXT: mulld r7, r8, r7
|
||||
; CHECK-BE-NEXT: sub r6, r6, r7
|
||||
; CHECK-BE-NEXT: stdux r5, r1, r6
|
||||
; CHECK-BE-NEXT: cmpd r1, r4
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB1_2
|
||||
; CHECK-BE-NEXT: .LBB1_1:
|
||||
; CHECK-BE-NEXT: stdu r5, -4096(r1)
|
||||
; CHECK-BE-NEXT: cmpd r1, r4
|
||||
; CHECK-BE-NEXT: bne cr0, .LBB1_1
|
||||
; CHECK-BE-NEXT: .LBB1_2:
|
||||
; CHECK-BE-NEXT: extsw r3, r3
|
||||
; CHECK-BE-NEXT: addi r4, r1, 48
|
||||
; CHECK-BE-NEXT: sldi r3, r3, 2
|
||||
; CHECK-BE-NEXT: li r5, 1
|
||||
; CHECK-BE-NEXT: add r3, r4, r3
|
||||
; CHECK-BE-NEXT: stw r5, 4096(r3)
|
||||
; CHECK-BE-NEXT: lwz r3, 0(r4)
|
||||
; CHECK-BE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-BE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
;
|
||||
; CHECK-32-LABEL: bar:
|
||||
; CHECK-32: # %bb.0:
|
||||
; CHECK-32-NEXT: stwu r1, -32(r1)
|
||||
; CHECK-32-NEXT: slwi r3, r3, 2
|
||||
; CHECK-32-NEXT: addi r4, r3, 15
|
||||
; CHECK-32-NEXT: rlwinm r4, r4, 0, 0, 27
|
||||
; CHECK-32-NEXT: neg r6, r4
|
||||
; CHECK-32-NEXT: li r7, -4096
|
||||
; CHECK-32-NEXT: divw r8, r6, r7
|
||||
; CHECK-32-NEXT: stw r31, 28(r1)
|
||||
; CHECK-32-NEXT: mr r31, r1
|
||||
; CHECK-32-NEXT: addi r5, r31, 32
|
||||
; CHECK-32-NEXT: add r4, r1, r6
|
||||
; CHECK-32-NEXT: mullw r7, r8, r7
|
||||
; CHECK-32-NEXT: sub r6, r6, r7
|
||||
; CHECK-32-NEXT: stwux r5, r1, r6
|
||||
; CHECK-32-NEXT: cmpw r1, r4
|
||||
; CHECK-32-NEXT: beq cr0, .LBB1_2
|
||||
; CHECK-32-NEXT: .LBB1_1:
|
||||
; CHECK-32-NEXT: stwu r5, -4096(r1)
|
||||
; CHECK-32-NEXT: cmpw r1, r4
|
||||
; CHECK-32-NEXT: bne cr0, .LBB1_1
|
||||
; CHECK-32-NEXT: .LBB1_2:
|
||||
; CHECK-32-NEXT: addi r4, r1, 16
|
||||
; CHECK-32-NEXT: li r5, 1
|
||||
; CHECK-32-NEXT: add r3, r4, r3
|
||||
; CHECK-32-NEXT: stw r5, 4096(r3)
|
||||
; CHECK-32-NEXT: lwz r3, 0(r4)
|
||||
; CHECK-32-NEXT: lwz r31, 0(r1)
|
||||
; CHECK-32-NEXT: lwz r0, -4(r31)
|
||||
; CHECK-32-NEXT: mr r1, r31
|
||||
; CHECK-32-NEXT: mr r31, r0
|
||||
; CHECK-32-NEXT: blr
|
||||
%a = alloca i32, i32 %n, align 16
|
||||
%i = add i32 %n, 1024
|
||||
%b = getelementptr inbounds i32, i32* %a, i32 %i
|
||||
store volatile i32 1, i32* %b
|
||||
%c = load volatile i32, i32* %a
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
define i32 @f(i32 %n) local_unnamed_addr #0 "stack-probe-size"="65536" nounwind {
|
||||
; CHECK-LE-LABEL: f:
|
||||
; CHECK-LE: # %bb.0:
|
||||
; CHECK-LE-NEXT: std r31, -8(r1)
|
||||
; CHECK-LE-NEXT: stdu r1, -48(r1)
|
||||
; CHECK-LE-NEXT: rldic r3, r3, 2, 30
|
||||
; CHECK-LE-NEXT: lis r5, -1
|
||||
; CHECK-LE-NEXT: mr r31, r1
|
||||
; CHECK-LE-NEXT: addi r3, r3, 15
|
||||
; CHECK-LE-NEXT: ori r5, r5, 0
|
||||
; CHECK-LE-NEXT: addi r4, r31, 48
|
||||
; CHECK-LE-NEXT: rldicl r3, r3, 60, 4
|
||||
; CHECK-LE-NEXT: rldicl r3, r3, 4, 29
|
||||
; CHECK-LE-NEXT: neg r6, r3
|
||||
; CHECK-LE-NEXT: divd r7, r6, r5
|
||||
; CHECK-LE-NEXT: add r3, r1, r6
|
||||
; CHECK-LE-NEXT: mulld r7, r7, r5
|
||||
; CHECK-LE-NEXT: sub r6, r6, r7
|
||||
; CHECK-LE-NEXT: stdux r4, r1, r6
|
||||
; CHECK-LE-NEXT: cmpd r1, r3
|
||||
; CHECK-LE-NEXT: beq cr0, .LBB2_2
|
||||
; CHECK-LE-NEXT: .LBB2_1:
|
||||
; CHECK-LE-NEXT: stdux r4, r1, r5
|
||||
; CHECK-LE-NEXT: cmpd r1, r3
|
||||
; CHECK-LE-NEXT: bne cr0, .LBB2_1
|
||||
; CHECK-LE-NEXT: .LBB2_2:
|
||||
; CHECK-LE-NEXT: li r4, 1
|
||||
; CHECK-LE-NEXT: addi r3, r1, 32
|
||||
; CHECK-LE-NEXT: stw r4, 4792(r3)
|
||||
; CHECK-LE-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-LE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-P9-LE-LABEL: f:
|
||||
; CHECK-P9-LE: # %bb.0:
|
||||
; CHECK-P9-LE-NEXT: std r31, -8(r1)
|
||||
; CHECK-P9-LE-NEXT: stdu r1, -48(r1)
|
||||
; CHECK-P9-LE-NEXT: rldic r3, r3, 2, 30
|
||||
; CHECK-P9-LE-NEXT: addi r3, r3, 15
|
||||
; CHECK-P9-LE-NEXT: rldicl r3, r3, 60, 4
|
||||
; CHECK-P9-LE-NEXT: rldicl r3, r3, 4, 29
|
||||
; CHECK-P9-LE-NEXT: lis r5, -1
|
||||
; CHECK-P9-LE-NEXT: ori r5, r5, 0
|
||||
; CHECK-P9-LE-NEXT: neg r6, r3
|
||||
; CHECK-P9-LE-NEXT: divd r7, r6, r5
|
||||
; CHECK-P9-LE-NEXT: mulld r7, r7, r5
|
||||
; CHECK-P9-LE-NEXT: mr r31, r1
|
||||
; CHECK-P9-LE-NEXT: addi r4, r31, 48
|
||||
; CHECK-P9-LE-NEXT: add r3, r1, r6
|
||||
; CHECK-P9-LE-NEXT: sub r6, r6, r7
|
||||
; CHECK-P9-LE-NEXT: stdux r4, r1, r6
|
||||
; CHECK-P9-LE-NEXT: cmpd r1, r3
|
||||
; CHECK-P9-LE-NEXT: beq cr0, .LBB2_2
|
||||
; CHECK-P9-LE-NEXT: .LBB2_1:
|
||||
; CHECK-P9-LE-NEXT: stdux r4, r1, r5
|
||||
; CHECK-P9-LE-NEXT: cmpd r1, r3
|
||||
; CHECK-P9-LE-NEXT: bne cr0, .LBB2_1
|
||||
; CHECK-P9-LE-NEXT: .LBB2_2:
|
||||
; CHECK-P9-LE-NEXT: addi r3, r1, 32
|
||||
; CHECK-P9-LE-NEXT: li r4, 1
|
||||
; CHECK-P9-LE-NEXT: stw r4, 4792(r3)
|
||||
; CHECK-P9-LE-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-P9-LE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-P9-LE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-P9-LE-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: f:
|
||||
; CHECK-BE: # %bb.0:
|
||||
; CHECK-BE-NEXT: std r31, -8(r1)
|
||||
; CHECK-BE-NEXT: stdu r1, -64(r1)
|
||||
; CHECK-BE-NEXT: rldic r3, r3, 2, 30
|
||||
; CHECK-BE-NEXT: lis r5, -1
|
||||
; CHECK-BE-NEXT: addi r3, r3, 15
|
||||
; CHECK-BE-NEXT: rldicl r3, r3, 60, 4
|
||||
; CHECK-BE-NEXT: ori r5, r5, 0
|
||||
; CHECK-BE-NEXT: rldicl r3, r3, 4, 29
|
||||
; CHECK-BE-NEXT: mr r31, r1
|
||||
; CHECK-BE-NEXT: neg r6, r3
|
||||
; CHECK-BE-NEXT: divd r7, r6, r5
|
||||
; CHECK-BE-NEXT: addi r4, r31, 64
|
||||
; CHECK-BE-NEXT: mulld r7, r7, r5
|
||||
; CHECK-BE-NEXT: add r3, r1, r6
|
||||
; CHECK-BE-NEXT: sub r6, r6, r7
|
||||
; CHECK-BE-NEXT: stdux r4, r1, r6
|
||||
; CHECK-BE-NEXT: cmpd r1, r3
|
||||
; CHECK-BE-NEXT: beq cr0, .LBB2_2
|
||||
; CHECK-BE-NEXT: .LBB2_1:
|
||||
; CHECK-BE-NEXT: stdux r4, r1, r5
|
||||
; CHECK-BE-NEXT: cmpd r1, r3
|
||||
; CHECK-BE-NEXT: bne cr0, .LBB2_1
|
||||
; CHECK-BE-NEXT: .LBB2_2:
|
||||
; CHECK-BE-NEXT: li r4, 1
|
||||
; CHECK-BE-NEXT: addi r3, r1, 48
|
||||
; CHECK-BE-NEXT: stw r4, 4792(r3)
|
||||
; CHECK-BE-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-BE-NEXT: ld r1, 0(r1)
|
||||
; CHECK-BE-NEXT: ld r31, -8(r1)
|
||||
; CHECK-BE-NEXT: blr
|
||||
;
|
||||
; CHECK-32-LABEL: f:
|
||||
; CHECK-32: # %bb.0:
|
||||
; CHECK-32-NEXT: stwu r1, -32(r1)
|
||||
; CHECK-32-NEXT: slwi r3, r3, 2
|
||||
; CHECK-32-NEXT: addi r3, r3, 15
|
||||
; CHECK-32-NEXT: rlwinm r3, r3, 0, 0, 27
|
||||
; CHECK-32-NEXT: lis r5, -1
|
||||
; CHECK-32-NEXT: neg r6, r3
|
||||
; CHECK-32-NEXT: ori r5, r5, 0
|
||||
; CHECK-32-NEXT: divw r7, r6, r5
|
||||
; CHECK-32-NEXT: stw r31, 28(r1)
|
||||
; CHECK-32-NEXT: mr r31, r1
|
||||
; CHECK-32-NEXT: addi r4, r31, 32
|
||||
; CHECK-32-NEXT: add r3, r1, r6
|
||||
; CHECK-32-NEXT: mullw r7, r7, r5
|
||||
; CHECK-32-NEXT: sub r6, r6, r7
|
||||
; CHECK-32-NEXT: stwux r4, r1, r6
|
||||
; CHECK-32-NEXT: cmpw r1, r3
|
||||
; CHECK-32-NEXT: beq cr0, .LBB2_2
|
||||
; CHECK-32-NEXT: .LBB2_1:
|
||||
; CHECK-32-NEXT: stwux r4, r1, r5
|
||||
; CHECK-32-NEXT: cmpw r1, r3
|
||||
; CHECK-32-NEXT: bne cr0, .LBB2_1
|
||||
; CHECK-32-NEXT: .LBB2_2:
|
||||
; CHECK-32-NEXT: li r4, 1
|
||||
; CHECK-32-NEXT: addi r3, r1, 16
|
||||
; CHECK-32-NEXT: stw r4, 4792(r3)
|
||||
; CHECK-32-NEXT: lwz r3, 0(r3)
|
||||
; CHECK-32-NEXT: lwz r31, 0(r1)
|
||||
; CHECK-32-NEXT: lwz r0, -4(r31)
|
||||
; CHECK-32-NEXT: mr r1, r31
|
||||
; CHECK-32-NEXT: mr r31, r0
|
||||
; CHECK-32-NEXT: blr
|
||||
%a = alloca i32, i32 %n, align 16
|
||||
%b = getelementptr inbounds i32, i32* %a, i64 1198
|
||||
store volatile i32 1, i32* %b
|
||||
%c = load volatile i32, i32* %a
|
||||
ret i32 %c
|
||||
}
|
||||
|
||||
attributes #0 = {"probe-stack"="inline-asm"}
|
||||
Loading…
Reference in New Issue