From 036242b8685402162f781eb1d97c4d60c6016c19 Mon Sep 17 00:00:00 2001
From: Jonas Paulsson <paulsson@linux.vnet.ibm.com>
Date: Wed, 15 Apr 2020 11:29:55 +0200
Subject: [PATCH] [SystemZ] Bugfix in adjustSubwordCmp()

adjustSubwordCmp() should not optimize a load of an i1 value. This is
achieved by checking that the size and store-size of the MemoryVT are the
same.

Fixes https://bugs.llvm.org/show_bug.cgi?id=45511.

Review: Ulrich Weigand

Differential Revision: https://reviews.llvm.org/D78187
---
 .../Target/SystemZ/SystemZISelLowering.cpp    |  5 ++--
 llvm/test/CodeGen/SystemZ/int-cmp-59.ll       | 28 +++++++++++++++++++
 2 files changed, 31 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/SystemZ/int-cmp-59.ll

diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 9e5d7f23cdb6..8e05e872074d 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -2051,8 +2051,9 @@ static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
 
   // We must have an 8- or 16-bit load.
   auto *Load = cast<LoadSDNode>(C.Op0);
-  unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
-  if (NumBits != 8 && NumBits != 16)
+  unsigned NumBits = Load->getMemoryVT().getSizeInBits();
+  if ((NumBits != 8 && NumBits != 16) ||
+      NumBits != Load->getMemoryVT().getStoreSizeInBits())
     return;
 
   // The load must be an extending one and the constant must be within the
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-59.ll b/llvm/test/CodeGen/SystemZ/int-cmp-59.ll
new file mode 100644
index 000000000000..85f4a6847310
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-59.ll
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 -stop-before=finalize-isel \
+; RUN:   | FileCheck %s
+;
+; Check that an i1 in memory used in a comparison is loaded correctly.
+
+@bPtr = external dso_local local_unnamed_addr global i32*, align 8
+@c = external hidden unnamed_addr global i1, align 4
+
+define i64 @main() {
+; CHECK-LABEL: bb.0.entry:
+; CHECK: %1:addr64bit = LARL @c
+; CHECK: %2:gr64bit = LLGC %1, 0, $noreg :: (dereferenceable load 1 from @c, align 4)
+; CHECK-NEXT: %4:gr64bit = IMPLICIT_DEF
+; CHECK-NEXT: %3:gr64bit = RISBGN %4, killed %2, 63, 191, 0
+; CHECK-NEXT: %5:gr64bit = LCGR killed %3, implicit-def dead $cc
+; CHECK-NEXT: CGHI killed %5, 1, implicit-def $cc
+entry:
+  %0 = load i32*, i32** @bPtr
+  store i1 true, i1* @c
+  store i32 8, i32* %0
+  %.b = load i1, i1* @c
+  %conv.i = select i1 %.b, i64 1, i64 3
+  %div.i = sdiv i64 -1, %conv.i
+  %cmp.i = icmp eq i64 %div.i, 1
+  %conv2.i = zext i1 %cmp.i to i64
+  ret i64 %conv2.i
+}
+