forked from OSchip/llvm-project
[SystemZ] Bugfix in adjustSubwordCmp()
adjustSubwordCmp() should not optimize a load of an i1 value. This is achieved by checking that the size and store-size of the MemoryVT are the same. Fixes https://bugs.llvm.org/show_bug.cgi?id=45511. Review: Ulrich Weigand Differential Revision: https://reviews.llvm.org/D78187
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@ -2051,8 +2051,9 @@ static void adjustSubwordCmp(SelectionDAG &DAG, const SDLoc &DL,
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// We must have an 8- or 16-bit load.
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auto *Load = cast<LoadSDNode>(C.Op0);
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unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
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if (NumBits != 8 && NumBits != 16)
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unsigned NumBits = Load->getMemoryVT().getSizeInBits();
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if ((NumBits != 8 && NumBits != 16) ||
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NumBits != Load->getMemoryVT().getStoreSizeInBits())
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return;
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// The load must be an extending one and the constant must be within the
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@ -0,0 +1,28 @@
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 -O3 -stop-before=finalize-isel \
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; RUN: | FileCheck %s
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;
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; Check that an i1 in memory used in a comparison is loaded correctly.
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@bPtr = external dso_local local_unnamed_addr global i32*, align 8
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@c = external hidden unnamed_addr global i1, align 4
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define i64 @main() {
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; CHECK-LABEL: bb.0.entry:
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; CHECK: %1:addr64bit = LARL @c
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; CHECK: %2:gr64bit = LLGC %1, 0, $noreg :: (dereferenceable load 1 from @c, align 4)
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; CHECK-NEXT: %4:gr64bit = IMPLICIT_DEF
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; CHECK-NEXT: %3:gr64bit = RISBGN %4, killed %2, 63, 191, 0
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; CHECK-NEXT: %5:gr64bit = LCGR killed %3, implicit-def dead $cc
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; CHECK-NEXT: CGHI killed %5, 1, implicit-def $cc
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entry:
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%0 = load i32*, i32** @bPtr
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store i1 true, i1* @c
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store i32 8, i32* %0
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%.b = load i1, i1* @c
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%conv.i = select i1 %.b, i64 1, i64 3
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%div.i = sdiv i64 -1, %conv.i
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%cmp.i = icmp eq i64 %div.i, 1
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%conv2.i = zext i1 %cmp.i to i64
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ret i64 %conv2.i
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}
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