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[X86] Add itineraries to ADD.*_DB instructions to match their normal counterparts. 

llvm-svn: 328352
This commit is contained in:
Craig Topper 2018-03-23 19:15:03 +00:00
parent 88441a3d1e
commit 02fb3907f1
1 changed files with 20 additions and 11 deletions
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31
llvm/lib/Target/X86/X86InstrCompiler.td
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@ -1340,13 +1340,16 @@ let isConvertibleToThreeAddress = 1,
let isCommutable = 1 in {
def ADD16rr_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"", // orw/addw REG, REG
[(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))]>;
[(set GR16:$dst, (or_is_add GR16:$src1, GR16:$src2))],
IIC_BIN_NONMEM>;
def ADD32rr_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"", // orl/addl REG, REG
[(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))]>;
[(set GR32:$dst, (or_is_add GR32:$src1, GR32:$src2))],
IIC_BIN_NONMEM>;
def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
"", // orq/addq REG, REG
[(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))]>;
[(set GR64:$dst, (or_is_add GR64:$src1, GR64:$src2))],
IIC_BIN_NONMEM>;
} // isCommutable
// NOTE: These are order specific, we want the ri8 forms to be listed
@ -1355,30 +1358,36 @@ def ADD64rr_DB : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
def ADD16ri8_DB : I<0, Pseudo,
(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
"", // orw/addw REG, imm8
[(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))]>;
[(set GR16:$dst,(or_is_add GR16:$src1,i16immSExt8:$src2))],
IIC_BIN_NONMEM>;
def ADD16ri_DB : I<0, Pseudo, (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2),
"", // orw/addw REG, imm
[(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))]>;
[(set GR16:$dst, (or_is_add GR16:$src1, imm:$src2))],
IIC_BIN_NONMEM>;
def ADD32ri8_DB : I<0, Pseudo,
(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
"", // orl/addl REG, imm8
[(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))]>;
[(set GR32:$dst,(or_is_add GR32:$src1,i32immSExt8:$src2))],
IIC_BIN_NONMEM>;
def ADD32ri_DB : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
"", // orl/addl REG, imm
[(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))]>;
[(set GR32:$dst, (or_is_add GR32:$src1, imm:$src2))],
IIC_BIN_NONMEM>;
def ADD64ri8_DB : I<0, Pseudo,
(outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2),
"", // orq/addq REG, imm8
[(set GR64:$dst, (or_is_add GR64:$src1,
i64immSExt8:$src2))]>;
i64immSExt8:$src2))],
IIC_BIN_NONMEM>;
def ADD64ri32_DB : I<0, Pseudo,
(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
"", // orq/addq REG, imm
[(set GR64:$dst, (or_is_add GR64:$src1,
i64immSExt32:$src2))]>;
"", // orq/addq REG, imm
[(set GR64:$dst, (or_is_add GR64:$src1,
i64immSExt32:$src2))],
IIC_BIN_NONMEM>;
}
} // AddedComplexity, SchedRW