forked from OSchip/llvm-project
[X86][AVX512] Passing the appropriate memory operand class to INT_{U}COMIS{S|D} instructions
Replacing the memory operand in the intrinsic versions of the comis/ucomis instrucions from f128mem to ssmem/sdmem accordingly. Differential Revision: https://reviews.llvm.org/D28138 llvm-svn: 290948
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c76ea4b638
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02f9533823
llvm/lib/Target/X86
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@ -6844,18 +6844,18 @@ let Defs = [EFLAGS], Predicates = [HasAVX512] in {
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VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
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}
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let isCodeGenOnly = 1 in {
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defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
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load, "ucomiss">, PS, EVEX, VEX_LIG,
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defm Int_VUCOMISSZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v4f32, ssmem,
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sse_load_f32, "ucomiss">, PS, EVEX, VEX_LIG,
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EVEX_CD8<32, CD8VT1>;
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defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
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load, "ucomisd">, PD, EVEX,
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defm Int_VUCOMISDZ : sse12_ord_cmp_int<0x2E, VR128X, X86ucomi, v2f64, sdmem,
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sse_load_f64, "ucomisd">, PD, EVEX,
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VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
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defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
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load, "comiss">, PS, EVEX, VEX_LIG,
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defm Int_VCOMISSZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v4f32, ssmem,
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sse_load_f32, "comiss">, PS, EVEX, VEX_LIG,
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EVEX_CD8<32, CD8VT1>;
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defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
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load, "comisd">, PD, EVEX,
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defm Int_VCOMISDZ : sse12_ord_cmp_int<0x2F, VR128X, X86comi, v2f64, sdmem,
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sse_load_f64, "comisd">, PD, EVEX,
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VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
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}
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}
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@ -2373,6 +2373,23 @@ multiclass sse12_ord_cmp<bits<8> opc, RegisterClass RC, SDNode OpNode,
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Sched<[WriteFAddLd, ReadAfterLd]>;
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}
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// sse12_ord_cmp_int - Intrinsic version of sse12_ord_cmp
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multiclass sse12_ord_cmp_int<bits<8> opc, RegisterClass RC, SDNode OpNode,
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ValueType vt, Operand memop,
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ComplexPattern mem_cpat, string OpcodeStr> {
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def rr: SI<opc, MRMSrcReg, (outs), (ins RC:$src1, RC:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (vt RC:$src1), RC:$src2))],
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IIC_SSE_COMIS_RR>,
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Sched<[WriteFAdd]>;
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def rm: SI<opc, MRMSrcMem, (outs), (ins RC:$src1, memop:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1|$src1, $src2}"),
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[(set EFLAGS, (OpNode (vt RC:$src1),
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mem_cpat:$src2))],
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IIC_SSE_COMIS_RM>,
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Sched<[WriteFAddLd, ReadAfterLd]>;
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}
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let Defs = [EFLAGS] in {
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defm VUCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
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"ucomiss">, PS, VEX, VEX_LIG;
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@ -2386,15 +2403,15 @@ let Defs = [EFLAGS] in {
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}
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let isCodeGenOnly = 1 in {
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defm Int_VUCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
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load, "ucomiss">, PS, VEX;
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defm Int_VUCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
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load, "ucomisd">, PD, VEX;
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defm Int_VUCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
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sse_load_f32, "ucomiss">, PS, VEX;
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defm Int_VUCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem,
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sse_load_f64, "ucomisd">, PD, VEX;
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defm Int_VCOMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem,
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load, "comiss">, PS, VEX;
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defm Int_VCOMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem,
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load, "comisd">, PD, VEX;
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defm Int_VCOMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem,
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sse_load_f32, "comiss">, PS, VEX;
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defm Int_VCOMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem,
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sse_load_f64, "comisd">, PD, VEX;
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}
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defm UCOMISS : sse12_ord_cmp<0x2E, FR32, X86cmp, f32, f32mem, loadf32,
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"ucomiss">, PS;
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@ -2409,15 +2426,15 @@ let Defs = [EFLAGS] in {
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}
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let isCodeGenOnly = 1 in {
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defm Int_UCOMISS : sse12_ord_cmp<0x2E, VR128, X86ucomi, v4f32, f128mem,
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load, "ucomiss">, PS;
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defm Int_UCOMISD : sse12_ord_cmp<0x2E, VR128, X86ucomi, v2f64, f128mem,
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load, "ucomisd">, PD;
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defm Int_UCOMISS : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v4f32, ssmem,
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sse_load_f32, "ucomiss">, PS;
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defm Int_UCOMISD : sse12_ord_cmp_int<0x2E, VR128, X86ucomi, v2f64, sdmem,
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sse_load_f64, "ucomisd">, PD;
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defm Int_COMISS : sse12_ord_cmp<0x2F, VR128, X86comi, v4f32, f128mem, load,
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"comiss">, PS;
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defm Int_COMISD : sse12_ord_cmp<0x2F, VR128, X86comi, v2f64, f128mem, load,
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"comisd">, PD;
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defm Int_COMISS : sse12_ord_cmp_int<0x2F, VR128, X86comi, v4f32, ssmem,
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sse_load_f32, "comiss">, PS;
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defm Int_COMISD : sse12_ord_cmp_int<0x2F, VR128, X86comi, v2f64, sdmem,
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sse_load_f64, "comisd">, PD;
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}
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} // Defs = [EFLAGS]
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