forked from OSchip/llvm-project
[X86] Make sure all the classes declare in the Haswell scheduler model are prefixed with HW.
The tablegen files all share a namespace so we shouldn't use a generic names in a specific scheduler model. llvm-svn: 328955
This commit is contained in:
Craig Topper
parent
c90d906b16
commit
02daec00a2
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@ -282,31 +282,31 @@ def : WriteRes<WriteNop, []>;
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//-- Specific Scheduling Models --//
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// Starting with P0.
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def WriteP0 : SchedWriteRes<[HWPort0]>;
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def HWWriteP0 : SchedWriteRes<[HWPort0]>;
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def WriteP01 : SchedWriteRes<[HWPort01]>;
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def HWWriteP01 : SchedWriteRes<[HWPort01]>;
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def Write2P01 : SchedWriteRes<[HWPort01]> {
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def HWWrite2P01 : SchedWriteRes<[HWPort01]> {
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let NumMicroOps = 2;
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}
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def Write3P01 : SchedWriteRes<[HWPort01]> {
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def HWWrite3P01 : SchedWriteRes<[HWPort01]> {
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let NumMicroOps = 3;
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}
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def WriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
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def HWWriteP0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
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let NumMicroOps = 2;
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}
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def Write2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
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def HWWrite2P0156_P23 : SchedWriteRes<[HWPort0156, HWPort23]> {
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let NumMicroOps = 3;
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let ResourceCycles = [2, 1];
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}
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// Starting with P1.
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def WriteP1 : SchedWriteRes<[HWPort1]>;
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def HWWriteP1 : SchedWriteRes<[HWPort1]>;
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def Write2P1 : SchedWriteRes<[HWPort1]> {
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def HWWrite2P1 : SchedWriteRes<[HWPort1]> {
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let NumMicroOps = 2;
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let ResourceCycles = [2];
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}
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@ -324,217 +324,217 @@ def Write2P1 : SchedWriteRes<[HWPort1]> {
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//-- Move instructions --//
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// XLAT.
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def WriteXLAT : SchedWriteRes<[]> {
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def HWWriteXLAT : SchedWriteRes<[]> {
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let Latency = 7;
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteXLAT], (instregex "XLAT")>;
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def : InstRW<[HWWriteXLAT], (instregex "XLAT")>;
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// PUSHA.
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def WritePushA : SchedWriteRes<[]> {
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def HWWritePushA : SchedWriteRes<[]> {
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let NumMicroOps = 19;
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}
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def : InstRW<[WritePushA], (instregex "PUSHA(16|32)")>;
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def : InstRW<[HWWritePushA], (instregex "PUSHA(16|32)")>;
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// POPA.
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def WritePopA : SchedWriteRes<[]> {
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def HWWritePopA : SchedWriteRes<[]> {
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let NumMicroOps = 18;
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}
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def : InstRW<[WritePopA], (instregex "POPA(16|32)")>;
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def : InstRW<[HWWritePopA], (instregex "POPA(16|32)")>;
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//-- Arithmetic instructions --//
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// DIV.
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// r8.
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def WriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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def HWWriteDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 22;
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let NumMicroOps = 9;
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}
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def : InstRW<[WriteDiv8], (instregex "DIV8r")>;
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def : InstRW<[HWWriteDiv8], (instregex "DIV8r")>;
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// IDIV.
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// r8.
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def WriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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def HWWriteIDiv8 : SchedWriteRes<[HWPort0, HWPort1, HWPort5, HWPort6]> {
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let Latency = 23;
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let NumMicroOps = 9;
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}
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def : InstRW<[WriteIDiv8], (instregex "IDIV8r")>;
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def : InstRW<[HWWriteIDiv8], (instregex "IDIV8r")>;
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// BT.
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// m,r.
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def WriteBTmr : SchedWriteRes<[]> {
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def HWWriteBTmr : SchedWriteRes<[]> {
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let NumMicroOps = 10;
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}
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def : InstRW<[WriteBTmr], (instregex "BT(16|32|64)mr")>;
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def : InstRW<[HWWriteBTmr], (instregex "BT(16|32|64)mr")>;
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// BTR BTS BTC.
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// m,r.
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def WriteBTRSCmr : SchedWriteRes<[]> {
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def HWWriteBTRSCmr : SchedWriteRes<[]> {
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let NumMicroOps = 11;
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}
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def : InstRW<[WriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
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def : InstRW<[HWWriteBTRSCmr], (instregex "BT(R|S|C)(16|32|64)mr")>;
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//-- Control transfer instructions --//
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// CALL.
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// i.
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def WriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
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def HWWriteRETI : SchedWriteRes<[HWPort23, HWPort6, HWPort015]> {
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let NumMicroOps = 4;
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let ResourceCycles = [1, 2, 1];
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}
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def : InstRW<[WriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
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def : InstRW<[HWWriteRETI], (instregex "RETI(L|Q|W)", "LRETI(L|Q|W)")>;
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// BOUND.
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// r,m.
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def WriteBOUND : SchedWriteRes<[]> {
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def HWWriteBOUND : SchedWriteRes<[]> {
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let NumMicroOps = 15;
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}
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def : InstRW<[WriteBOUND], (instregex "BOUNDS(16|32)rm")>;
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def : InstRW<[HWWriteBOUND], (instregex "BOUNDS(16|32)rm")>;
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// INTO.
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def WriteINTO : SchedWriteRes<[]> {
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def HWWriteINTO : SchedWriteRes<[]> {
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let NumMicroOps = 4;
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}
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def : InstRW<[WriteINTO], (instregex "INTO")>;
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def : InstRW<[HWWriteINTO], (instregex "INTO")>;
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//-- String instructions --//
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// LODSB/W.
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def : InstRW<[Write2P0156_P23], (instregex "LODS(B|W)")>;
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def : InstRW<[HWWrite2P0156_P23], (instregex "LODS(B|W)")>;
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// LODSD/Q.
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def : InstRW<[WriteP0156_P23], (instregex "LODS(L|Q)")>;
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def : InstRW<[HWWriteP0156_P23], (instregex "LODS(L|Q)")>;
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// MOVS.
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def WriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
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def HWWriteMOVS : SchedWriteRes<[HWPort23, HWPort4, HWPort0156]> {
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let Latency = 4;
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let NumMicroOps = 5;
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let ResourceCycles = [2, 1, 2];
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}
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def : InstRW<[WriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
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def : InstRW<[HWWriteMOVS], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
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// CMPS.
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def WriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
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def HWWriteCMPS : SchedWriteRes<[HWPort23, HWPort0156]> {
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let Latency = 4;
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let NumMicroOps = 5;
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let ResourceCycles = [2, 3];
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}
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def : InstRW<[WriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
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def : InstRW<[HWWriteCMPS], (instregex "CMPS(B|L|Q|W)")>;
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//-- Other --//
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// RDPMC.f
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def WriteRDPMC : SchedWriteRes<[]> {
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def HWWriteRDPMC : SchedWriteRes<[]> {
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let NumMicroOps = 34;
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}
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def : InstRW<[WriteRDPMC], (instregex "RDPMC")>;
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def : InstRW<[HWWriteRDPMC], (instregex "RDPMC")>;
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// RDRAND.
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def WriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
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def HWWriteRDRAND : SchedWriteRes<[HWPort23, HWPort015]> {
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let NumMicroOps = 17;
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let ResourceCycles = [1, 16];
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}
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def : InstRW<[WriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
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def : InstRW<[HWWriteRDRAND], (instregex "RDRAND(16|32|64)r")>;
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//=== Floating Point x87 Instructions ===//
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//-- Move instructions --//
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// FLD.
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// m80.
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def : InstRW<[WriteP01], (instregex "LD_Frr")>;
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def : InstRW<[HWWriteP01], (instregex "LD_Frr")>;
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// FBLD.
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// m80.
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def WriteFBLD : SchedWriteRes<[]> {
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def HWWriteFBLD : SchedWriteRes<[]> {
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let Latency = 47;
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let NumMicroOps = 43;
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}
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def : InstRW<[WriteFBLD], (instregex "FBLDm")>;
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def : InstRW<[HWWriteFBLD], (instregex "FBLDm")>;
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// FST(P).
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// r.
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def : InstRW<[WriteP01], (instregex "ST_(F|FP)rr")>;
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def : InstRW<[HWWriteP01], (instregex "ST_(F|FP)rr")>;
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// FLDZ.
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def : InstRW<[WriteP01], (instregex "LD_F0")>;
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def : InstRW<[HWWriteP01], (instregex "LD_F0")>;
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// FLDPI FLDL2E etc.
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def : InstRW<[Write2P01], (instregex "FLDPI", "FLDL2(T|E)", "FLDL(G|N)2")>;
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def : InstRW<[HWWrite2P01], (instregex "FLDPI", "FLDL2(T|E)", "FLDL(G|N)2")>;
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// FFREE.
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def : InstRW<[WriteP01], (instregex "FFREE")>;
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def : InstRW<[HWWriteP01], (instregex "FFREE")>;
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// FNSAVE.
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def WriteFNSAVE : SchedWriteRes<[]> {
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def HWWriteFNSAVE : SchedWriteRes<[]> {
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let NumMicroOps = 147;
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}
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def : InstRW<[WriteFNSAVE], (instregex "FSAVEm")>;
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def : InstRW<[HWWriteFNSAVE], (instregex "FSAVEm")>;
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// FRSTOR.
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def WriteFRSTOR : SchedWriteRes<[]> {
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def HWWriteFRSTOR : SchedWriteRes<[]> {
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let NumMicroOps = 90;
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}
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def : InstRW<[WriteFRSTOR], (instregex "FRSTORm")>;
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def : InstRW<[HWWriteFRSTOR], (instregex "FRSTORm")>;
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//-- Arithmetic instructions --//
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// FABS.
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def : InstRW<[WriteP0], (instregex "ABS_F")>;
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def : InstRW<[HWWriteP0], (instregex "ABS_F")>;
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// FCHS.
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def : InstRW<[WriteP0], (instregex "CHS_F")>;
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def : InstRW<[HWWriteP0], (instregex "CHS_F")>;
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// FCOMPP FUCOMPP.
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// r.
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def : InstRW<[Write2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
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def : InstRW<[HWWrite2P01], (instregex "FCOMPP", "UCOM_FPPr")>;
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// FCOMI(P) FUCOMI(P).
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// m.
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def : InstRW<[Write3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
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"UCOM_FIPr")>;
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def : InstRW<[HWWrite3P01], (instregex "COM_FIr", "COM_FIPr", "UCOM_FIr",
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"UCOM_FIPr")>;
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// FTST.
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def : InstRW<[WriteP1], (instregex "TST_F")>;
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def : InstRW<[HWWriteP1], (instregex "TST_F")>;
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// FXAM.
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def : InstRW<[Write2P1], (instregex "FXAM")>;
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def : InstRW<[HWWrite2P1], (instregex "FXAM")>;
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// FPREM.
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def WriteFPREM : SchedWriteRes<[]> {
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def HWWriteFPREM : SchedWriteRes<[]> {
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let Latency = 19;
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let NumMicroOps = 28;
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}
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def : InstRW<[WriteFPREM], (instrs FPREM)>;
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def : InstRW<[HWWriteFPREM], (instrs FPREM)>;
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// FPREM1.
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def WriteFPREM1 : SchedWriteRes<[]> {
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def HWWriteFPREM1 : SchedWriteRes<[]> {
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let Latency = 27;
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let NumMicroOps = 41;
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}
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def : InstRW<[WriteFPREM1], (instrs FPREM1)>;
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def : InstRW<[HWWriteFPREM1], (instrs FPREM1)>;
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// FRNDINT.
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def WriteFRNDINT : SchedWriteRes<[]> {
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def HWWriteFRNDINT : SchedWriteRes<[]> {
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let Latency = 11;
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let NumMicroOps = 17;
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}
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def : InstRW<[WriteFRNDINT], (instregex "FRNDINT")>;
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def : InstRW<[HWWriteFRNDINT], (instregex "FRNDINT")>;
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//-- Math instructions --//
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// FSCALE.
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def WriteFSCALE : SchedWriteRes<[]> {
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def HWWriteFSCALE : SchedWriteRes<[]> {
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let Latency = 75; // 49-125
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let NumMicroOps = 50; // 25-75
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}
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def : InstRW<[WriteFSCALE], (instregex "FSCALE")>;
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def : InstRW<[HWWriteFSCALE], (instregex "FSCALE")>;
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// FXTRACT.
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def WriteFXTRACT : SchedWriteRes<[]> {
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def HWWriteFXTRACT : SchedWriteRes<[]> {
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let Latency = 15;
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let NumMicroOps = 17;
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}
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def : InstRW<[WriteFXTRACT], (instregex "FXTRACT")>;
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def : InstRW<[HWWriteFXTRACT], (instregex "FXTRACT")>;
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////////////////////////////////////////////////////////////////////////////////
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// Horizontal add/sub instructions.
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