forked from OSchip/llvm-project
R600/SI: Fix using mad with multiplies by 2
These turn into fadds, so combine them into the target mad node. fadd (fadd (a, a), b) -> mad 2.0, a, b llvm-svn: 218608
This commit is contained in:
Matt Arsenault
parent
70d54ac848
commit
02cb0ff7db
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@ -226,6 +226,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::FDIV, MVT::f32, Custom);
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setTargetDAGCombine(ISD::FADD);
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setTargetDAGCombine(ISD::FSUB);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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@ -1418,6 +1419,40 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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case ISD::UINT_TO_FP: {
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return performUCharToFloatCombine(N, DCI);
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case ISD::FADD: {
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if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
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break;
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EVT VT = N->getValueType(0);
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if (VT != MVT::f32)
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break;
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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// These should really be instruction patterns, but writing patterns with
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// source modiifiers is a pain.
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// fadd (fadd (a, a), b) -> mad 2.0, a, b
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if (LHS.getOpcode() == ISD::FADD) {
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SDValue A = LHS.getOperand(0);
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if (A == LHS.getOperand(1)) {
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const SDValue Two = DAG.getTargetConstantFP(2.0, MVT::f32);
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, RHS);
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}
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}
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// fadd (b, fadd (a, a)) -> mad 2.0, a, b
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if (RHS.getOpcode() == ISD::FADD) {
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SDValue A = RHS.getOperand(0);
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if (A == RHS.getOperand(1)) {
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const SDValue Two = DAG.getTargetConstantFP(2.0, MVT::f32);
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return DAG.getNode(AMDGPUISD::MAD, DL, VT, Two, A, LHS);
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}
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}
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break;
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}
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case ISD::FSUB: {
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if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
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break;
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@ -1,6 +1,11 @@
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; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
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; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck %s
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; CHECK: @fmuladd_f32
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declare float @llvm.fmuladd.f32(float, float, float)
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declare double @llvm.fmuladd.f64(double, double, double)
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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declare float @llvm.fabs.f32(float) nounwind readnone
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; CHECK-LABEL: @fmuladd_f32
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; CHECK: V_MAD_F32 {{v[0-9]+, v[0-9]+, v[0-9]+, v[0-9]+}}
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define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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@ -13,9 +18,7 @@ define void @fmuladd_f32(float addrspace(1)* %out, float addrspace(1)* %in1,
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ret void
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}
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declare float @llvm.fmuladd.f32(float, float, float)
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; CHECK: @fmuladd_f64
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; CHECK-LABEL: @fmuladd_f64
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; CHECK: V_FMA_F64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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@ -28,4 +31,147 @@ define void @fmuladd_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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ret void
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}
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declare double @llvm.fmuladd.f64(double, double, double)
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; CHECK-LABEL: @fmuladd_2.0_a_b_f32
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
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; CHECK: BUFFER_STORE_DWORD [[RESULT]]
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define void @fmuladd_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%r1 = load float addrspace(1)* %gep.0
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%r2 = load float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: @fmuladd_a_2.0_b_f32
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
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; CHECK: BUFFER_STORE_DWORD [[RESULT]]
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define void @fmuladd_a_2.0_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%r1 = load float addrspace(1)* %gep.0
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%r2 = load float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float %r1, float 2.0, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: @fadd_a_a_b_f32
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
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; CHECK: BUFFER_STORE_DWORD [[RESULT]]
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define void @fadd_a_a_b_f32(float addrspace(1)* %out,
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float addrspace(1)* %in1,
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float addrspace(1)* %in2) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%r0 = load float addrspace(1)* %gep.0
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%r1 = load float addrspace(1)* %gep.1
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%add.0 = fadd float %r0, %r0
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%add.1 = fadd float %add.0, %r1
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store float %add.1, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: @fadd_b_a_a_f32
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
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; CHECK: BUFFER_STORE_DWORD [[RESULT]]
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define void @fadd_b_a_a_f32(float addrspace(1)* %out,
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float addrspace(1)* %in1,
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float addrspace(1)* %in2) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%r0 = load float addrspace(1)* %gep.0
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%r1 = load float addrspace(1)* %gep.1
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%add.0 = fadd float %r0, %r0
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%add.1 = fadd float %r1, %add.0
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store float %add.1, float addrspace(1)* %out
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ret void
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}
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; CHECK-LABEL: @fmuladd_neg_2.0_a_b_f32
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]]
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; CHECK: BUFFER_STORE_DWORD [[RESULT]]
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define void @fmuladd_neg_2.0_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%r1 = load float addrspace(1)* %gep.0
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%r2 = load float addrspace(1)* %gep.1
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%r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: @fmuladd_neg_2.0_neg_a_b_f32
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], 2.0, [[R1]], [[R2]]
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; CHECK: BUFFER_STORE_DWORD [[RESULT]]
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define void @fmuladd_neg_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%r1 = load float addrspace(1)* %gep.0
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%r2 = load float addrspace(1)* %gep.1
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%r1.fneg = fsub float -0.000000e+00, %r1
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%r3 = tail call float @llvm.fmuladd.f32(float -2.0, float %r1.fneg, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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; CHECK-LABEL: @fmuladd_2.0_neg_a_b_f32
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
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; CHECK-DAG: BUFFER_LOAD_DWORD [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:0x4
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; CHECK: V_MAD_F32 [[RESULT:v[0-9]+]], [[R1]], -2.0, [[R2]]
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; CHECK: BUFFER_STORE_DWORD [[RESULT]]
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define void @fmuladd_2.0_neg_a_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep.0 = getelementptr float addrspace(1)* %out, i32 %tid
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%gep.1 = getelementptr float addrspace(1)* %gep.0, i32 1
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%gep.out = getelementptr float addrspace(1)* %out, i32 %tid
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%r1 = load float addrspace(1)* %gep.0
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%r2 = load float addrspace(1)* %gep.1
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%r1.fneg = fsub float -0.000000e+00, %r1
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%r3 = tail call float @llvm.fmuladd.f32(float 2.0, float %r1.fneg, float %r2)
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store float %r3, float addrspace(1)* %gep.out
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ret void
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}
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