forked from OSchip/llvm-project
Revert "[VP,Integer,#2] ExpandVectorPredication pass"
This reverts commit 43bc584dc0.
The commit broke the -DLLVM_ENABLE_MODULES=1 builds.
http://green.lab.llvm.org/green/view/LLDB/job/lldb-cmake/31603/consoleFull#2136199809a1ca8a51-895e-46c6-af87-ce24fa4cd561
This commit is contained in:
Adrian Prantl
parent
b11e4c9907
commit
02c5ba8679
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@ -61,7 +61,6 @@ class TargetLibraryInfo;
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class Type;
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class User;
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class Value;
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class VPIntrinsic;
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struct KnownBits;
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template <typename T> class Optional;
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@ -1380,38 +1379,6 @@ public:
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/// Intrinsics") Use of %evl is discouraged when that is not the case.
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bool hasActiveVectorLength() const;
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struct VPLegalization {
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enum VPTransform {
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// keep the predicating parameter
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Legal = 0,
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// where legal, discard the predicate parameter
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Discard = 1,
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// transform into something else that is also predicating
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Convert = 2
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};
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// How to transform the EVL parameter.
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// Legal: keep the EVL parameter as it is.
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// Discard: Ignore the EVL parameter where it is safe to do so.
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// Convert: Fold the EVL into the mask parameter.
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VPTransform EVLParamStrategy;
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// How to transform the operator.
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// Legal: The target supports this operator.
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// Convert: Convert this to a non-VP operation.
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// The 'Discard' strategy is invalid.
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VPTransform OpStrategy;
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bool shouldDoNothing() const {
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return (EVLParamStrategy == Legal) && (OpStrategy == Legal);
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}
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VPLegalization(VPTransform EVLParamStrategy, VPTransform OpStrategy)
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: EVLParamStrategy(EVLParamStrategy), OpStrategy(OpStrategy) {}
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};
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/// \returns How the target needs this vector-predicated operation to be
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/// transformed.
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VPLegalization getVPLegalizationStrategy(const VPIntrinsic &PI) const;
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/// @}
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/// @}
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@ -1721,8 +1688,6 @@ public:
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virtual bool supportsScalableVectors() const = 0;
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virtual bool hasActiveVectorLength() const = 0;
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virtual InstructionCost getInstructionLatency(const Instruction *I) = 0;
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virtual VPLegalization
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getVPLegalizationStrategy(const VPIntrinsic &PI) const = 0;
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};
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template <typename T>
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@ -2294,11 +2259,6 @@ public:
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InstructionCost getInstructionLatency(const Instruction *I) override {
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return Impl.getInstructionLatency(I);
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}
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VPLegalization
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getVPLegalizationStrategy(const VPIntrinsic &PI) const override {
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return Impl.getVPLegalizationStrategy(PI);
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}
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};
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template <typename T>
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@ -750,13 +750,6 @@ public:
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bool hasActiveVectorLength() const { return false; }
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TargetTransformInfo::VPLegalization
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getVPLegalizationStrategy(const VPIntrinsic &PI) const {
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return TargetTransformInfo::VPLegalization(
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/* EVLParamStrategy */ TargetTransformInfo::VPLegalization::Discard,
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/* OperatorStrategy */ TargetTransformInfo::VPLegalization::Convert);
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}
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protected:
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// Obtain the minimum required size to hold the value (without the sign)
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// In case of a vector it returns the min required size for one element.
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@ -1,23 +0,0 @@
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//===-- ExpandVectorPredication.h - Expand vector predication ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_EXPANDVECTORPREDICATION_H
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#define LLVM_CODEGEN_EXPANDVECTORPREDICATION_H
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#include "llvm/IR/PassManager.h"
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namespace llvm {
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class ExpandVectorPredicationPass
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: public PassInfoMixin<ExpandVectorPredicationPass> {
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public:
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PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
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};
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} // end namespace llvm
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#endif // LLVM_CODEGEN_EXPANDVECTORPREDICATION_H
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@ -103,7 +103,6 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (
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#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR)
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#endif
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DUMMY_FUNCTION_PASS("expandmemcmp", ExpandMemCmpPass, ())
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DUMMY_FUNCTION_PASS("expandvp", ExpandVectorPredicationPass, ())
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DUMMY_FUNCTION_PASS("gc-lowering", GCLoweringPass, ())
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DUMMY_FUNCTION_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ())
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DUMMY_FUNCTION_PASS("sjljehprepare", SjLjEHPreparePass, ())
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@ -453,11 +453,6 @@ namespace llvm {
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// the corresponding function in a vector library (e.g., SVML, libmvec).
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FunctionPass *createReplaceWithVeclibLegacyPass();
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/// This pass expands the vector predication intrinsics into unpredicated
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/// instructions with selects or just the explicit vector length into the
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/// predicate mask.
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FunctionPass *createExpandVectorPredicationPass();
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// This pass expands memcmp() to load/stores.
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FunctionPass *createExpandMemCmpPass();
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@ -400,11 +400,9 @@ public:
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/// \return the mask parameter or nullptr.
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Value *getMaskParam() const;
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void setMaskParam(Value *);
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/// \return the vector length parameter or nullptr.
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Value *getVectorLengthParam() const;
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void setVectorLengthParam(Value *);
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/// \return whether the vector length param can be ignored.
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bool canIgnoreVectorLengthParam() const;
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@ -154,7 +154,6 @@ void initializeEntryExitInstrumenterPass(PassRegistry&);
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void initializeExpandMemCmpPassPass(PassRegistry&);
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void initializeExpandPostRAPass(PassRegistry&);
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void initializeExpandReductionsPass(PassRegistry&);
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void initializeExpandVectorPredicationPass(PassRegistry &);
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void initializeMakeGuardsExplicitLegacyPassPass(PassRegistry&);
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void initializeExternalAAWrapperPassPass(PassRegistry&);
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void initializeFEntryInserterPass(PassRegistry&);
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@ -197,7 +197,6 @@ namespace {
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(void) llvm::createMergeFunctionsPass();
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(void) llvm::createMergeICmpsLegacyPass();
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(void) llvm::createExpandMemCmpPass();
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(void) llvm::createExpandVectorPredicationPass();
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std::string buf;
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llvm::raw_string_ostream os(buf);
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(void) llvm::createPrintModulePass(os);
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@ -1026,11 +1026,6 @@ bool TargetTransformInfo::preferPredicatedReductionSelect(
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return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
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}
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TargetTransformInfo::VPLegalization
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TargetTransformInfo::getVPLegalizationStrategy(const VPIntrinsic &VPI) const {
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return TTIImpl->getVPLegalizationStrategy(VPI);
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}
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bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
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return TTIImpl->shouldExpandReduction(II);
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}
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@ -29,7 +29,6 @@ add_llvm_component_library(LLVMCodeGen
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ExpandMemCmp.cpp
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ExpandPostRAPseudos.cpp
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ExpandReductions.cpp
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ExpandVectorPredication.cpp
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FaultMaps.cpp
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FEntryInserter.cpp
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FinalizeISel.cpp
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@ -1,469 +0,0 @@
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//===----- CodeGen/ExpandVectorPredication.cpp - Expand VP intrinsics -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass implements IR expansion for vector predication intrinsics, allowing
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// targets to enable vector predication until just before codegen.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/ExpandVectorPredication.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Constants.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/IRBuilder.h"
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#include "llvm/IR/InstIterator.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/IntrinsicInst.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Module.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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using VPLegalization = TargetTransformInfo::VPLegalization;
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using VPTransform = TargetTransformInfo::VPLegalization::VPTransform;
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// Keep this in sync with TargetTransformInfo::VPLegalization.
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#define VPINTERNAL_VPLEGAL_CASES \
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VPINTERNAL_CASE(Legal) \
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VPINTERNAL_CASE(Discard) \
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VPINTERNAL_CASE(Convert)
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#define VPINTERNAL_CASE(X) "|" #X
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// Override options.
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static cl::opt<std::string> EVLTransformOverride(
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"expandvp-override-evl-transform", cl::init(""), cl::Hidden,
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cl::desc("Options: <empty>" VPINTERNAL_VPLEGAL_CASES
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". If non-empty, ignore "
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"TargetTransformInfo and "
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"always use this transformation for the %evl parameter (Used in "
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"testing)."));
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static cl::opt<std::string> MaskTransformOverride(
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"expandvp-override-mask-transform", cl::init(""), cl::Hidden,
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cl::desc("Options: <empty>" VPINTERNAL_VPLEGAL_CASES
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". If non-empty, Ignore "
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"TargetTransformInfo and "
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"always use this transformation for the %mask parameter (Used in "
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"testing)."));
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#undef VPINTERNAL_CASE
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#define VPINTERNAL_CASE(X) .Case(#X, VPLegalization::X)
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static VPTransform parseOverrideOption(const std::string &TextOpt) {
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return StringSwitch<VPTransform>(TextOpt) VPINTERNAL_VPLEGAL_CASES;
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}
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#undef VPINTERNAL_VPLEGAL_CASES
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// Whether any override options are set.
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static bool anyExpandVPOverridesSet() {
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return !EVLTransformOverride.empty() || !MaskTransformOverride.empty();
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}
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#define DEBUG_TYPE "expandvp"
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STATISTIC(NumFoldedVL, "Number of folded vector length params");
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STATISTIC(NumLoweredVPOps, "Number of folded vector predication operations");
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///// Helpers {
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/// \returns Whether the vector mask \p MaskVal has all lane bits set.
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static bool isAllTrueMask(Value *MaskVal) {
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auto *ConstVec = dyn_cast<ConstantVector>(MaskVal);
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return ConstVec && ConstVec->isAllOnesValue();
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}
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/// \returns A non-excepting divisor constant for this type.
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static Constant *getSafeDivisor(Type *DivTy) {
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assert(DivTy->isIntOrIntVectorTy() && "Unsupported divisor type");
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return ConstantInt::get(DivTy, 1u, false);
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}
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/// Transfer operation properties from \p OldVPI to \p NewVal.
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static void transferDecorations(Value &NewVal, VPIntrinsic &VPI) {
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auto *NewInst = dyn_cast<Instruction>(&NewVal);
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if (!NewInst || !isa<FPMathOperator>(NewVal))
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return;
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auto *OldFMOp = dyn_cast<FPMathOperator>(&VPI);
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if (!OldFMOp)
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return;
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NewInst->setFastMathFlags(OldFMOp->getFastMathFlags());
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}
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/// Transfer all properties from \p OldOp to \p NewOp and replace all uses.
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/// OldVP gets erased.
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static void replaceOperation(Value &NewOp, VPIntrinsic &OldOp) {
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transferDecorations(NewOp, OldOp);
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OldOp.replaceAllUsesWith(&NewOp);
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OldOp.eraseFromParent();
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}
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//// } Helpers
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namespace {
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// Expansion pass state at function scope.
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struct CachingVPExpander {
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Function &F;
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const TargetTransformInfo &TTI;
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/// \returns A (fixed length) vector with ascending integer indices
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/// (<0, 1, ..., NumElems-1>).
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/// \p Builder
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/// Used for instruction creation.
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/// \p LaneTy
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/// Integer element type of the result vector.
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/// \p NumElems
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/// Number of vector elements.
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Value *createStepVector(IRBuilder<> &Builder, Type *LaneTy,
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unsigned NumElems);
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/// \returns A bitmask that is true where the lane position is less-than \p
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/// EVLParam
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///
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/// \p Builder
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/// Used for instruction creation.
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/// \p VLParam
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/// The explicit vector length parameter to test against the lane
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/// positions.
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/// \p ElemCount
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/// Static (potentially scalable) number of vector elements.
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Value *convertEVLToMask(IRBuilder<> &Builder, Value *EVLParam,
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ElementCount ElemCount);
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Value *foldEVLIntoMask(VPIntrinsic &VPI);
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/// "Remove" the %evl parameter of \p PI by setting it to the static vector
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/// length of the operation.
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void discardEVLParameter(VPIntrinsic &PI);
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/// \brief Lower this VP binary operator to a unpredicated binary operator.
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Value *expandPredicationInBinaryOperator(IRBuilder<> &Builder,
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VPIntrinsic &PI);
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/// \brief Query TTI and expand the vector predication in \p P accordingly.
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Value *expandPredication(VPIntrinsic &PI);
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/// \brief Determine how and whether the VPIntrinsic \p VPI shall be
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/// expanded. This overrides TTI with the cl::opts listed at the top of this
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/// file.
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VPLegalization getVPLegalizationStrategy(const VPIntrinsic &VPI) const;
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bool UsingTTIOverrides;
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public:
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CachingVPExpander(Function &F, const TargetTransformInfo &TTI)
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: F(F), TTI(TTI), UsingTTIOverrides(anyExpandVPOverridesSet()) {}
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bool expandVectorPredication();
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};
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//// CachingVPExpander {
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Value *CachingVPExpander::createStepVector(IRBuilder<> &Builder, Type *LaneTy,
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unsigned NumElems) {
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// TODO add caching
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SmallVector<Constant *, 16> ConstElems;
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for (unsigned Idx = 0; Idx < NumElems; ++Idx)
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ConstElems.push_back(ConstantInt::get(LaneTy, Idx, false));
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return ConstantVector::get(ConstElems);
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}
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Value *CachingVPExpander::convertEVLToMask(IRBuilder<> &Builder,
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Value *EVLParam,
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ElementCount ElemCount) {
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// TODO add caching
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// Scalable vector %evl conversion.
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if (ElemCount.isScalable()) {
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auto *M = Builder.GetInsertBlock()->getModule();
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Type *BoolVecTy = VectorType::get(Builder.getInt1Ty(), ElemCount);
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Function *ActiveMaskFunc = Intrinsic::getDeclaration(
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M, Intrinsic::get_active_lane_mask, {BoolVecTy, EVLParam->getType()});
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// `get_active_lane_mask` performs an implicit less-than comparison.
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Value *ConstZero = Builder.getInt32(0);
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return Builder.CreateCall(ActiveMaskFunc, {ConstZero, EVLParam});
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}
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// Fixed vector %evl conversion.
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Type *LaneTy = EVLParam->getType();
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unsigned NumElems = ElemCount.getFixedValue();
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Value *VLSplat = Builder.CreateVectorSplat(NumElems, EVLParam);
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Value *IdxVec = createStepVector(Builder, LaneTy, NumElems);
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return Builder.CreateICmp(CmpInst::ICMP_ULT, IdxVec, VLSplat);
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}
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Value *
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CachingVPExpander::expandPredicationInBinaryOperator(IRBuilder<> &Builder,
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VPIntrinsic &VPI) {
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assert((isSafeToSpeculativelyExecute(&VPI) ||
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VPI.canIgnoreVectorLengthParam()) &&
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"Implicitly dropping %evl in non-speculatable operator!");
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auto OC = static_cast<Instruction::BinaryOps>(VPI.getFunctionalOpcode());
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assert(Instruction::isBinaryOp(OC));
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Value *Op0 = VPI.getOperand(0);
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Value *Op1 = VPI.getOperand(1);
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Value *Mask = VPI.getMaskParam();
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// Blend in safe operands.
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if (Mask && !isAllTrueMask(Mask)) {
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switch (OC) {
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default:
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// Can safely ignore the predicate.
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break;
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// Division operators need a safe divisor on masked-off lanes (1).
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case Instruction::UDiv:
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case Instruction::SDiv:
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case Instruction::URem:
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case Instruction::SRem:
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// 2nd operand must not be zero.
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Value *SafeDivisor = getSafeDivisor(VPI.getType());
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Op1 = Builder.CreateSelect(Mask, Op1, SafeDivisor);
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}
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}
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Value *NewBinOp = Builder.CreateBinOp(OC, Op0, Op1, VPI.getName());
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replaceOperation(*NewBinOp, VPI);
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return NewBinOp;
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}
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void CachingVPExpander::discardEVLParameter(VPIntrinsic &VPI) {
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LLVM_DEBUG(dbgs() << "Discard EVL parameter in " << VPI << "\n");
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if (VPI.canIgnoreVectorLengthParam())
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return;
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Value *EVLParam = VPI.getVectorLengthParam();
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if (!EVLParam)
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return;
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ElementCount StaticElemCount = VPI.getStaticVectorLength();
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Value *MaxEVL = nullptr;
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Type *Int32Ty = Type::getInt32Ty(VPI.getContext());
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if (StaticElemCount.isScalable()) {
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// TODO add caching
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auto *M = VPI.getModule();
|
||||
Function *VScaleFunc =
|
||||
Intrinsic::getDeclaration(M, Intrinsic::vscale, Int32Ty);
|
||||
IRBuilder<> Builder(VPI.getParent(), VPI.getIterator());
|
||||
Value *FactorConst = Builder.getInt32(StaticElemCount.getKnownMinValue());
|
||||
Value *VScale = Builder.CreateCall(VScaleFunc, {}, "vscale");
|
||||
MaxEVL = Builder.CreateMul(VScale, FactorConst, "scalable_size",
|
||||
/*NUW*/ true, /*NSW*/ false);
|
||||
} else {
|
||||
MaxEVL = ConstantInt::get(Int32Ty, StaticElemCount.getFixedValue(), false);
|
||||
}
|
||||
VPI.setVectorLengthParam(MaxEVL);
|
||||
}
|
||||
|
||||
Value *CachingVPExpander::foldEVLIntoMask(VPIntrinsic &VPI) {
|
||||
LLVM_DEBUG(dbgs() << "Folding vlen for " << VPI << '\n');
|
||||
|
||||
IRBuilder<> Builder(&VPI);
|
||||
|
||||
// Ineffective %evl parameter and so nothing to do here.
|
||||
if (VPI.canIgnoreVectorLengthParam())
|
||||
return &VPI;
|
||||
|
||||
// Only VP intrinsics can have an %evl parameter.
|
||||
Value *OldMaskParam = VPI.getMaskParam();
|
||||
Value *OldEVLParam = VPI.getVectorLengthParam();
|
||||
assert(OldMaskParam && "no mask param to fold the vl param into");
|
||||
assert(OldEVLParam && "no EVL param to fold away");
|
||||
|
||||
LLVM_DEBUG(dbgs() << "OLD evl: " << *OldEVLParam << '\n');
|
||||
LLVM_DEBUG(dbgs() << "OLD mask: " << *OldMaskParam << '\n');
|
||||
|
||||
// Convert the %evl predication into vector mask predication.
|
||||
ElementCount ElemCount = VPI.getStaticVectorLength();
|
||||
Value *VLMask = convertEVLToMask(Builder, OldEVLParam, ElemCount);
|
||||
Value *NewMaskParam = Builder.CreateAnd(VLMask, OldMaskParam);
|
||||
VPI.setMaskParam(NewMaskParam);
|
||||
|
||||
// Drop the %evl parameter.
|
||||
discardEVLParameter(VPI);
|
||||
assert(VPI.canIgnoreVectorLengthParam() &&
|
||||
"transformation did not render the evl param ineffective!");
|
||||
|
||||
// Reassess the modified instruction.
|
||||
return &VPI;
|
||||
}
|
||||
|
||||
Value *CachingVPExpander::expandPredication(VPIntrinsic &VPI) {
|
||||
LLVM_DEBUG(dbgs() << "Lowering to unpredicated op: " << VPI << '\n');
|
||||
|
||||
IRBuilder<> Builder(&VPI);
|
||||
|
||||
// Try lowering to a LLVM instruction first.
|
||||
unsigned OC = VPI.getFunctionalOpcode();
|
||||
|
||||
if (Instruction::isBinaryOp(OC))
|
||||
return expandPredicationInBinaryOperator(Builder, VPI);
|
||||
|
||||
return &VPI;
|
||||
}
|
||||
|
||||
//// } CachingVPExpander
|
||||
|
||||
struct TransformJob {
|
||||
VPIntrinsic *PI;
|
||||
TargetTransformInfo::VPLegalization Strategy;
|
||||
TransformJob(VPIntrinsic *PI, TargetTransformInfo::VPLegalization InitStrat)
|
||||
: PI(PI), Strategy(InitStrat) {}
|
||||
|
||||
bool isDone() const { return Strategy.shouldDoNothing(); }
|
||||
};
|
||||
|
||||
void sanitizeStrategy(Instruction &I, VPLegalization &LegalizeStrat) {
|
||||
// Speculatable instructions do not strictly need predication.
|
||||
if (isSafeToSpeculativelyExecute(&I)) {
|
||||
// Converting a speculatable VP intrinsic means dropping %mask and %evl.
|
||||
// No need to expand %evl into the %mask only to ignore that code.
|
||||
if (LegalizeStrat.OpStrategy == VPLegalization::Convert)
|
||||
LegalizeStrat.EVLParamStrategy = VPLegalization::Discard;
|
||||
return;
|
||||
}
|
||||
|
||||
// We have to preserve the predicating effect of %evl for this
|
||||
// non-speculatable VP intrinsic.
|
||||
// 1) Never discard %evl.
|
||||
// 2) If this VP intrinsic will be expanded to non-VP code, make sure that
|
||||
// %evl gets folded into %mask.
|
||||
if ((LegalizeStrat.EVLParamStrategy == VPLegalization::Discard) ||
|
||||
(LegalizeStrat.OpStrategy == VPLegalization::Convert)) {
|
||||
LegalizeStrat.EVLParamStrategy = VPLegalization::Convert;
|
||||
}
|
||||
}
|
||||
|
||||
VPLegalization
|
||||
CachingVPExpander::getVPLegalizationStrategy(const VPIntrinsic &VPI) const {
|
||||
auto VPStrat = TTI.getVPLegalizationStrategy(VPI);
|
||||
if (LLVM_LIKELY(!UsingTTIOverrides)) {
|
||||
// No overrides - we are in production.
|
||||
return VPStrat;
|
||||
}
|
||||
|
||||
// Overrides set - we are in testing, the following does not need to be
|
||||
// efficient.
|
||||
VPStrat.EVLParamStrategy = parseOverrideOption(EVLTransformOverride);
|
||||
VPStrat.OpStrategy = parseOverrideOption(MaskTransformOverride);
|
||||
return VPStrat;
|
||||
}
|
||||
|
||||
/// \brief Expand llvm.vp.* intrinsics as requested by \p TTI.
|
||||
bool CachingVPExpander::expandVectorPredication() {
|
||||
SmallVector<TransformJob, 16> Worklist;
|
||||
|
||||
// Collect all VPIntrinsics that need expansion and determine their expansion
|
||||
// strategy.
|
||||
for (auto &I : instructions(F)) {
|
||||
auto *VPI = dyn_cast<VPIntrinsic>(&I);
|
||||
if (!VPI)
|
||||
continue;
|
||||
auto VPStrat = getVPLegalizationStrategy(*VPI);
|
||||
sanitizeStrategy(I, VPStrat);
|
||||
if (!VPStrat.shouldDoNothing())
|
||||
Worklist.emplace_back(VPI, VPStrat);
|
||||
}
|
||||
if (Worklist.empty())
|
||||
return false;
|
||||
|
||||
// Transform all VPIntrinsics on the worklist.
|
||||
LLVM_DEBUG(dbgs() << "\n:::: Transforming " << Worklist.size()
|
||||
<< " instructions ::::\n");
|
||||
for (TransformJob Job : Worklist) {
|
||||
// Transform the EVL parameter.
|
||||
switch (Job.Strategy.EVLParamStrategy) {
|
||||
case VPLegalization::Legal:
|
||||
break;
|
||||
case VPLegalization::Discard:
|
||||
discardEVLParameter(*Job.PI);
|
||||
break;
|
||||
case VPLegalization::Convert:
|
||||
if (foldEVLIntoMask(*Job.PI))
|
||||
++NumFoldedVL;
|
||||
break;
|
||||
}
|
||||
Job.Strategy.EVLParamStrategy = VPLegalization::Legal;
|
||||
|
||||
// Replace with a non-predicated operation.
|
||||
switch (Job.Strategy.OpStrategy) {
|
||||
case VPLegalization::Legal:
|
||||
break;
|
||||
case VPLegalization::Discard:
|
||||
llvm_unreachable("Invalid strategy for operators.");
|
||||
case VPLegalization::Convert:
|
||||
expandPredication(*Job.PI);
|
||||
++NumLoweredVPOps;
|
||||
break;
|
||||
}
|
||||
Job.Strategy.OpStrategy = VPLegalization::Legal;
|
||||
|
||||
assert(Job.isDone() && "incomplete transformation");
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
class ExpandVectorPredication : public FunctionPass {
|
||||
public:
|
||||
static char ID;
|
||||
ExpandVectorPredication() : FunctionPass(ID) {
|
||||
initializeExpandVectorPredicationPass(*PassRegistry::getPassRegistry());
|
||||
}
|
||||
|
||||
bool runOnFunction(Function &F) override {
|
||||
const auto *TTI = &getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
|
||||
CachingVPExpander VPExpander(F, *TTI);
|
||||
return VPExpander.expandVectorPredication();
|
||||
}
|
||||
|
||||
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
||||
AU.addRequired<TargetTransformInfoWrapperPass>();
|
||||
AU.setPreservesCFG();
|
||||
}
|
||||
};
|
||||
} // namespace
|
||||
|
||||
char ExpandVectorPredication::ID;
|
||||
INITIALIZE_PASS_BEGIN(ExpandVectorPredication, "expandvp",
|
||||
"Expand vector predication intrinsics", false, false)
|
||||
INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
|
||||
INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
|
||||
INITIALIZE_PASS_END(ExpandVectorPredication, "expandvp",
|
||||
"Expand vector predication intrinsics", false, false)
|
||||
|
||||
FunctionPass *llvm::createExpandVectorPredicationPass() {
|
||||
return new ExpandVectorPredication();
|
||||
}
|
||||
|
||||
PreservedAnalyses
|
||||
ExpandVectorPredicationPass::run(Function &F, FunctionAnalysisManager &AM) {
|
||||
const auto &TTI = AM.getResult<TargetIRAnalysis>(F);
|
||||
CachingVPExpander VPExpander(F, TTI);
|
||||
if (!VPExpander.expandVectorPredication())
|
||||
return PreservedAnalyses::all();
|
||||
PreservedAnalyses PA;
|
||||
PA.preserveSet<CFGAnalyses>();
|
||||
return PA;
|
||||
}
|
||||
|
|
@ -864,11 +864,6 @@ void TargetPassConfig::addIRPasses() {
|
|||
if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
|
||||
addPass(createPartiallyInlineLibCallsPass());
|
||||
|
||||
// Expand vector predication intrinsics into standard IR instructions.
|
||||
// This pass has to run before ScalarizeMaskedMemIntrin and ExpandReduction
|
||||
// passes since it emits those kinds of intrinsics.
|
||||
addPass(createExpandVectorPredicationPass());
|
||||
|
||||
// Add scalarization of target's unsupported masked memory intrinsics pass.
|
||||
// the unsupported intrinsic will be replaced with a chain of basic blocks,
|
||||
// that stores/loads element one-by-one if the appropriate mask bit is set.
|
||||
|
|
|
|||
|
|
@ -279,11 +279,6 @@ Value *VPIntrinsic::getMaskParam() const {
|
|||
return nullptr;
|
||||
}
|
||||
|
||||
void VPIntrinsic::setMaskParam(Value *NewMask) {
|
||||
auto MaskPos = GetMaskParamPos(getIntrinsicID());
|
||||
setArgOperand(*MaskPos, NewMask);
|
||||
}
|
||||
|
||||
Value *VPIntrinsic::getVectorLengthParam() const {
|
||||
auto vlenPos = GetVectorLengthParamPos(getIntrinsicID());
|
||||
if (vlenPos)
|
||||
|
|
@ -291,11 +286,6 @@ Value *VPIntrinsic::getVectorLengthParam() const {
|
|||
return nullptr;
|
||||
}
|
||||
|
||||
void VPIntrinsic::setVectorLengthParam(Value *NewEVL) {
|
||||
auto EVLPos = GetVectorLengthParamPos(getIntrinsicID());
|
||||
setArgOperand(*EVLPos, NewEVL);
|
||||
}
|
||||
|
||||
Optional<int> VPIntrinsic::GetMaskParamPos(Intrinsic::ID IntrinsicID) {
|
||||
switch (IntrinsicID) {
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -21,7 +21,6 @@
|
|||
; CHECK-NEXT: Shadow Stack GC Lowering
|
||||
; CHECK-NEXT: Lower constant intrinsics
|
||||
; CHECK-NEXT: Remove unreachable blocks from the CFG
|
||||
; CHECK-NEXT: Expand vector predication intrinsics
|
||||
; CHECK-NEXT: Scalarize Masked Memory Intrinsics
|
||||
; CHECK-NEXT: Expand reduction intrinsics
|
||||
; CHECK-NEXT: AArch64 Stack Tagging
|
||||
|
|
|
|||
|
|
@ -56,7 +56,6 @@
|
|||
; CHECK-NEXT: Constant Hoisting
|
||||
; CHECK-NEXT: Replace intrinsics with calls to vector library
|
||||
; CHECK-NEXT: Partially inline calls to library functions
|
||||
; CHECK-NEXT: Expand vector predication intrinsics
|
||||
; CHECK-NEXT: Scalarize Masked Memory Intrinsics
|
||||
; CHECK-NEXT: Expand reduction intrinsics
|
||||
; CHECK-NEXT: Stack Safety Analysis
|
||||
|
|
|
|||
|
|
@ -37,7 +37,6 @@
|
|||
; CHECK-NEXT: Constant Hoisting
|
||||
; CHECK-NEXT: Replace intrinsics with calls to vector library
|
||||
; CHECK-NEXT: Partially inline calls to library functions
|
||||
; CHECK-NEXT: Expand vector predication intrinsics
|
||||
; CHECK-NEXT: Scalarize Masked Memory Intrinsics
|
||||
; CHECK-NEXT: Expand reduction intrinsics
|
||||
; CHECK-NEXT: Natural Loop Information
|
||||
|
|
|
|||
|
|
@ -1,245 +0,0 @@
|
|||
; Partial expansion cases (still VP with parameter expansions).
|
||||
; RUN: opt --expandvp --expandvp-override-evl-transform=Legal --expandvp-override-mask-transform=Legal -S < %s | FileCheck %s --check-prefix=LEGAL_LEGAL
|
||||
; RUN: opt --expandvp --expandvp-override-evl-transform=Discard --expandvp-override-mask-transform=Legal -S < %s | FileCheck %s --check-prefix=DISCARD_LEGAL
|
||||
; RUN: opt --expandvp --expandvp-override-evl-transform=Convert --expandvp-override-mask-transform=Legal -S < %s | FileCheck %s --check-prefix=CONVERT_LEGAL
|
||||
; Full expansion cases (all expanded to non-VP).
|
||||
; RUN: opt --expandvp --expandvp-override-evl-transform=Discard --expandvp-override-mask-transform=Convert -S < %s | FileCheck %s --check-prefix=ALL-CONVERT
|
||||
; RUN: opt --expandvp -S < %s | FileCheck %s --check-prefix=ALL-CONVERT
|
||||
; RUN: opt --expandvp --expandvp-override-evl-transform=Legal --expandvp-override-mask-transform=Convert -S < %s | FileCheck %s --check-prefix=ALL-CONVERT
|
||||
; RUN: opt --expandvp --expandvp-override-evl-transform=Convert --expandvp-override-mask-transform=Convert -S < %s | FileCheck %s --check-prefix=ALL-CONVERT
|
||||
|
||||
|
||||
; Fixed-width vectors
|
||||
; Integer arith
|
||||
declare <8 x i32> @llvm.vp.add.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.sub.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.mul.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.srem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.urem.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
; Bit arith
|
||||
declare <8 x i32> @llvm.vp.and.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.xor.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.or.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
declare <8 x i32> @llvm.vp.shl.v8i32(<8 x i32>, <8 x i32>, <8 x i1>, i32)
|
||||
|
||||
; Fixed vector test function.
|
||||
define void @test_vp_int_v8(<8 x i32> %i0, <8 x i32> %i1, <8 x i32> %i2, <8 x i32> %f3, <8 x i1> %m, i32 %n) {
|
||||
%r0 = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r1 = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r2 = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r3 = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r4 = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r5 = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r6 = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r7 = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r8 = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%r9 = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%rA = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%rB = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
%rC = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
ret void
|
||||
}
|
||||
|
||||
; Scalable-width vectors
|
||||
; Integer arith
|
||||
declare <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.sub.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.mul.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.sdiv.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.srem.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.udiv.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.urem.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
; Bit arith
|
||||
declare <vscale x 4 x i32> @llvm.vp.and.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.or.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.lshr.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
declare <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i1>, i32)
|
||||
|
||||
; Scalable vector test function.
|
||||
define void @test_vp_int_vscale(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i32> %i2, <vscale x 4 x i32> %f3, <vscale x 4 x i1> %m, i32 %n) {
|
||||
%r0 = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r1 = call <vscale x 4 x i32> @llvm.vp.sub.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r2 = call <vscale x 4 x i32> @llvm.vp.mul.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r3 = call <vscale x 4 x i32> @llvm.vp.sdiv.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r4 = call <vscale x 4 x i32> @llvm.vp.srem.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r5 = call <vscale x 4 x i32> @llvm.vp.udiv.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r6 = call <vscale x 4 x i32> @llvm.vp.urem.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r7 = call <vscale x 4 x i32> @llvm.vp.and.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r8 = call <vscale x 4 x i32> @llvm.vp.or.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%r9 = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%rA = call <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%rB = call <vscale x 4 x i32> @llvm.vp.lshr.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
%rC = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
ret void
|
||||
}
|
||||
; All VP intrinsics have to be lowered into non-VP ops
|
||||
; Convert %evl into %mask for non-speculatable VP intrinsics and emit the
|
||||
; instruction+select idiom with a non-VP SIMD instruction.
|
||||
;
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.add}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.sub}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.mul}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.sdiv}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.srem}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.udiv}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.urem}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.and}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.or}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.xor}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.ashr}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.lshr}}
|
||||
; ALL-CONVERT-NOT: {{call.* @llvm.vp.shl}}
|
||||
;
|
||||
; ALL-CONVERT: define void @test_vp_int_v8(<8 x i32> %i0, <8 x i32> %i1, <8 x i32> %i2, <8 x i32> %f3, <8 x i1> %m, i32 %n) {
|
||||
; ALL-CONVERT-NEXT: %{{.*}} = add <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT-NEXT: %{{.*}} = sub <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT-NEXT: %{{.*}} = mul <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT-NEXT: [[NINS:%.+]] = insertelement <8 x i32> poison, i32 %n, i32 0
|
||||
; ALL-CONVERT-NEXT: [[NSPLAT:%.+]] = shufflevector <8 x i32> [[NINS]], <8 x i32> poison, <8 x i32> zeroinitializer
|
||||
; ALL-CONVERT-NEXT: [[EVLM:%.+]] = icmp ult <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[NSPLAT]]
|
||||
; ALL-CONVERT-NEXT: [[NEWM:%.+]] = and <8 x i1> [[EVLM]], %m
|
||||
; ALL-CONVERT-NEXT: [[SELONE:%.+]] = select <8 x i1> [[NEWM]], <8 x i32> %i1, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
|
||||
; ALL-CONVERT-NEXT: %{{.+}} = sdiv <8 x i32> %i0, [[SELONE]]
|
||||
; ALL-CONVERT-NOT: %{{.+}} = srem <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT: %{{.+}} = srem <8 x i32> %i0, %{{.+}}
|
||||
; ALL-CONVERT-NOT: %{{.+}} = udiv <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT: %{{.+}} = udiv <8 x i32> %i0, %{{.+}}
|
||||
; ALL-CONVERT-NOT: %{{.+}} = urem <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT: %{{.+}} = urem <8 x i32> %i0, %{{.+}}
|
||||
; ALL-CONVERT-NEXT: %{{.+}} = and <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT-NEXT: %{{.+}} = or <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT-NEXT: %{{.+}} = xor <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT-NEXT: %{{.+}} = ashr <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT-NEXT: %{{.+}} = lshr <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT-NEXT: %{{.+}} = shl <8 x i32> %i0, %i1
|
||||
; ALL-CONVERT: ret void
|
||||
|
||||
|
||||
|
||||
|
||||
; All legal - don't transform anything.
|
||||
|
||||
; LEGAL_LEGAL: define void @test_vp_int_v8(<8 x i32> %i0, <8 x i32> %i1, <8 x i32> %i2, <8 x i32> %f3, <8 x i1> %m, i32 %n) {
|
||||
; LEGAL_LEGAL-NEXT: %r0 = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r1 = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r2 = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r3 = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r4 = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r5 = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r6 = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r7 = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r8 = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r9 = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %rA = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %rB = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %rC = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: ret void
|
||||
|
||||
; LEGAL_LEGAL:define void @test_vp_int_vscale(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i32> %i2, <vscale x 4 x i32> %f3, <vscale x 4 x i1> %m, i32 %n) {
|
||||
; LEGAL_LEGAL-NEXT: %r0 = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r1 = call <vscale x 4 x i32> @llvm.vp.sub.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r2 = call <vscale x 4 x i32> @llvm.vp.mul.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r3 = call <vscale x 4 x i32> @llvm.vp.sdiv.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r4 = call <vscale x 4 x i32> @llvm.vp.srem.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r5 = call <vscale x 4 x i32> @llvm.vp.udiv.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r6 = call <vscale x 4 x i32> @llvm.vp.urem.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r7 = call <vscale x 4 x i32> @llvm.vp.and.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r8 = call <vscale x 4 x i32> @llvm.vp.or.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %r9 = call <vscale x 4 x i32> @llvm.vp.xor.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %rA = call <vscale x 4 x i32> @llvm.vp.ashr.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %rB = call <vscale x 4 x i32> @llvm.vp.lshr.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: %rC = call <vscale x 4 x i32> @llvm.vp.shl.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %n)
|
||||
; LEGAL_LEGAL-NEXT: ret void
|
||||
|
||||
|
||||
; Drop %evl where possible else fold %evl into %mask (%evl Discard, %mask Legal)
|
||||
;
|
||||
; There is no caching yet in the ExpandVectorPredication pass and the %evl
|
||||
; expansion code is emitted for every non-speculatable intrinsic again. Hence,
|
||||
; only check that..
|
||||
; (1) The %evl folding code and %mask are correct for the first
|
||||
; non-speculatable VP intrinsic.
|
||||
; (2) All other non-speculatable VP intrinsics have a modified mask argument.
|
||||
; (3) All speculatable VP intrinsics keep their %mask and %evl.
|
||||
; (4) All VP intrinsics have an ineffective %evl parameter.
|
||||
|
||||
; DISCARD_LEGAL: define void @test_vp_int_v8(<8 x i32> %i0, <8 x i32> %i1, <8 x i32> %i2, <8 x i32> %f3, <8 x i1> %m, i32 %n) {
|
||||
; DISCARD_LEGAL-NEXT: %r0 = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: %r1 = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: %r2 = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: [[NSPLATINS:%.+]] = insertelement <8 x i32> poison, i32 %n, i32 0
|
||||
; DISCARD_LEGAL-NEXT: [[NSPLAT:%.+]] = shufflevector <8 x i32> [[NSPLATINS]], <8 x i32> poison, <8 x i32> zeroinitializer
|
||||
; DISCARD_LEGAL-NEXT: [[EVLMASK:%.+]] = icmp ult <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[NSPLAT]]
|
||||
; DISCARD_LEGAL-NEXT: [[NEWMASK:%.+]] = and <8 x i1> [[EVLMASK]], %m
|
||||
; DISCARD_LEGAL-NEXT: %r3 = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> [[NEWMASK]], i32 8)
|
||||
; DISCARD_LEGAL-NOT: %r4 = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NOT: %r5 = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NOT: %r6 = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL: %r7 = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: %r8 = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: %r9 = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: %rA = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: %rB = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: %rC = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; DISCARD_LEGAL-NEXT: ret void
|
||||
|
||||
; TODO compute vscale only once and use caching.
|
||||
; In the meantime, we only check for the correct vscale code for the first VP
|
||||
; intrinsic and skip over it for all others.
|
||||
|
||||
; DISCARD_LEGAL: define void @test_vp_int_vscale(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i32> %i2, <vscale x 4 x i32> %f3, <vscale x 4 x i1> %m, i32 %n) {
|
||||
; DISCARD_LEGAL-NEXT: %vscale = call i32 @llvm.vscale.i32()
|
||||
; DISCARD_LEGAL-NEXT: %scalable_size = mul nuw i32 %vscale, 4
|
||||
; DISCARD_LEGAL-NEXT: %r0 = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %scalable_size)
|
||||
; DISCARD_LEGAL: %r1 = call <vscale x 4 x i32> @llvm.vp.sub.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %scalable_size{{.*}})
|
||||
; DISCARD_LEGAL: %r2 = call <vscale x 4 x i32> @llvm.vp.mul.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> %m, i32 %scalable_size{{.*}})
|
||||
; DISCARD_LEGAL: [[EVLM:%.+]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 %n)
|
||||
; DISCARD_LEGAL: [[NEWM:%.+]] = and <vscale x 4 x i1> [[EVLM]], %m
|
||||
; DISCARD_LEGAL: %r3 = call <vscale x 4 x i32> @llvm.vp.sdiv.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> [[NEWM]], i32 %scalable_size{{.*}})
|
||||
; DISCARD_LEGAL-NOT: %{{.+}} = call <vscale x 4 x i32> @llvm.vp.{{.*}}, i32 %n)
|
||||
; DISCARD_LEGAL: ret void
|
||||
|
||||
|
||||
; Convert %evl into %mask everywhere (%evl Convert, %mask Legal)
|
||||
;
|
||||
; For the same reasons as in the (%evl Discard, %mask Legal) case only check that..
|
||||
; (1) The %evl folding code and %mask are correct for the first VP intrinsic.
|
||||
; (2) All other VP intrinsics have a modified mask argument.
|
||||
; (3) All VP intrinsics have an ineffective %evl parameter.
|
||||
;
|
||||
; CONVERT_LEGAL: define void @test_vp_int_v8(<8 x i32> %i0, <8 x i32> %i1, <8 x i32> %i2, <8 x i32> %f3, <8 x i1> %m, i32 %n) {
|
||||
; CONVERT_LEGAL-NEXT: [[NINS:%.+]] = insertelement <8 x i32> poison, i32 %n, i32 0
|
||||
; CONVERT_LEGAL-NEXT: [[NSPLAT:%.+]] = shufflevector <8 x i32> [[NINS]], <8 x i32> poison, <8 x i32> zeroinitializer
|
||||
; CONVERT_LEGAL-NEXT: [[EVLM:%.+]] = icmp ult <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, [[NSPLAT]]
|
||||
; CONVERT_LEGAL-NEXT: [[NEWM:%.+]] = and <8 x i1> [[EVLM]], %m
|
||||
; CONVERT_LEGAL-NEXT: %{{.+}} = call <8 x i32> @llvm.vp.add.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> [[NEWM]], i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.sub.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.mul.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.sdiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.srem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.udiv.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.urem.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.and.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.or.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.xor.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.ashr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.lshr.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL-NOT: %{{.+}} = call <8 x i32> @llvm.vp.shl.v8i32(<8 x i32> %i0, <8 x i32> %i1, <8 x i1> %m, i32 8)
|
||||
; CONVERT_LEGAL: ret void
|
||||
|
||||
; Similar to %evl discard, %mask legal but make sure the first VP intrinsic has a legal expansion
|
||||
; CONVERT_LEGAL: define void @test_vp_int_vscale(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i32> %i2, <vscale x 4 x i32> %f3, <vscale x 4 x i1> %m, i32 %n) {
|
||||
; CONVERT_LEGAL-NEXT: [[EVLM:%.+]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 %n)
|
||||
; CONVERT_LEGAL-NEXT: [[NEWM:%.+]] = and <vscale x 4 x i1> [[EVLM]], %m
|
||||
; CONVERT_LEGAL-NEXT: %vscale = call i32 @llvm.vscale.i32()
|
||||
; CONVERT_LEGAL-NEXT: %scalable_size = mul nuw i32 %vscale, 4
|
||||
; CONVERT_LEGAL-NEXT: %r0 = call <vscale x 4 x i32> @llvm.vp.add.nxv4i32(<vscale x 4 x i32> %i0, <vscale x 4 x i32> %i1, <vscale x 4 x i1> [[NEWM]], i32 %scalable_size)
|
||||
; CONVERT_LEGAL-NOT: %{{.*}} = call <vscale x 4 x i32> @llvm.vp.{{.*}}, i32 %n)
|
||||
; CONVERT_LEGAL: ret void
|
||||
|
||||
|
|
@ -25,7 +25,6 @@
|
|||
; CHECK-NEXT: Shadow Stack GC Lowering
|
||||
; CHECK-NEXT: Lower constant intrinsics
|
||||
; CHECK-NEXT: Remove unreachable blocks from the CFG
|
||||
; CHECK-NEXT: Expand vector predication intrinsics
|
||||
; CHECK-NEXT: Scalarize Masked Memory Intrinsics
|
||||
; CHECK-NEXT: Expand reduction intrinsics
|
||||
; CHECK-NEXT: Expand indirectbr instructions
|
||||
|
|
|
|||
|
|
@ -54,7 +54,6 @@
|
|||
; CHECK-NEXT: Constant Hoisting
|
||||
; CHECK-NEXT: Replace intrinsics with calls to vector library
|
||||
; CHECK-NEXT: Partially inline calls to library functions
|
||||
; CHECK-NEXT: Expand vector predication intrinsics
|
||||
; CHECK-NEXT: Scalarize Masked Memory Intrinsics
|
||||
; CHECK-NEXT: Expand reduction intrinsics
|
||||
; CHECK-NEXT: Interleaved Access Pass
|
||||
|
|
|
|||
|
|
@ -352,7 +352,6 @@ int main(int argc, char **argv) {
|
|||
initializeVectorization(*Registry);
|
||||
initializeScalarizeMaskedMemIntrinLegacyPassPass(*Registry);
|
||||
initializeExpandReductionsPass(*Registry);
|
||||
initializeExpandVectorPredicationPass(*Registry);
|
||||
initializeHardwareLoopsPass(*Registry);
|
||||
initializeTransformUtils(*Registry);
|
||||
initializeReplaceWithVeclibLegacyPass(*Registry);
|
||||
|
|
|
|||
|
|
@ -513,7 +513,7 @@ static bool shouldPinPassToLegacyPM(StringRef Pass) {
|
|||
"safe-stack", "cost-model",
|
||||
"codegenprepare", "interleaved-load-combine",
|
||||
"unreachableblockelim", "verify-safepoint-ir",
|
||||
"atomic-expand", "expandvp",
|
||||
"atomic-expand",
|
||||
"hardware-loops", "type-promotion",
|
||||
"mve-tail-predication", "interleaved-access",
|
||||
"global-merge", "pre-isel-intrinsic-lowering",
|
||||
|
|
@ -591,7 +591,6 @@ int main(int argc, char **argv) {
|
|||
initializePostInlineEntryExitInstrumenterPass(Registry);
|
||||
initializeUnreachableBlockElimLegacyPassPass(Registry);
|
||||
initializeExpandReductionsPass(Registry);
|
||||
initializeExpandVectorPredicationPass(Registry);
|
||||
initializeWasmEHPreparePass(Registry);
|
||||
initializeWriteBitcodePassPass(Registry);
|
||||
initializeHardwareLoopsPass(Registry);
|
||||
|
|
|
|||
Loading…
Reference in New Issue