[Docs] Remove some WIP X86 documentation I accidentally leaked into r328031.

I didn't mean to commit it, but I guess I failed to switch branches or stash it in my local tree.

llvm-svn: 328124

llvm/docs/CodeGenerator.rst

@@ -2656,9 +2656,3 @@ The AMDGPU backend
 The AMDGPU code generator lives in the ``lib/Target/AMDGPU``
 directory. This code generator is capable of targeting a variety of
 AMD GPU processors. Refer to :doc:`AMDGPUUsage` for more information.
-
-The X86 backend
-------------------
-
-The X86 code generator lives in the ``lib/Target/X86``
-directory. Refer to :doc:`X86Usage` for more information.

llvm/docs/CompilerWriterInfo.rst

@@ -99,8 +99,6 @@ X86
 * `X86 and X86-64 SysV psABI <https://github.com/hjl-tools/x86-psABI/wiki/X86-psABI>`_
 * `Calling conventions for different C++ compilers and operating systems  <http://www.agner.org/optimize/calling_conventions.pdf>`_
 
-Refer to :doc:`X86Usage` for additional documentation.
-
 XCore
 -----
 

llvm/docs/X86Usage.rst

@@ -1,85 +0,0 @@
-==========================
-User Guide for X86 Backend
-==========================
-
-.. contents::
-   :local:
-
-Introduction
-============
-
-The X86 backend provides ISA code generation for X86 CPUs. It lives in the
-``lib/Target/X86`` directory.
-
-LLVM
-====
-
-.. _x86-processors:
-
-Processors
-----------
-
-Use the ``clang -march=<Processor>`` option to specify the X86 processor.
-
-  .. table:: X86 processors
-     :name: x86-processor-table
-
-     ================== ===================
-     Processor          Alternative
-                        Name
-     ``i386``
-     ``i486``
-     ``i586``
-     ``pentium``
-     ``pentium-mmx``
-     ``i686``
-     ``pentiumpro``
-     ``pentium2``
-     ``pentium3``       - ``pentium3m``
-     ``pentium-m``
-     ``pentium4``       - ``pentium4m``
-     ``lakemont``
-     ``yonah``
-     ``prescott``
-     ``nocona``
-     ``core2``
-     ``penryn``
-     ``bonnell``        - ``atom``
-     ``silvermont``     - ``slm``
-     ``goldmont``
-     ``nehalem``        - ``corei7``
-     ``westmere``
-     ``sandybridge``    - ``corei7-avx``
-     ``ivybridge``      - ``core-avx-i``
-     ``haswell``        - ``core-avx2``
-     ``broadwell``      - ``skylake``
-     ``knl``
-     ``knm``
-     ``skylake-avx512`` - ``skx``
-     ``cannonlake``
-     ``icelake``
-     ``k6``
-     ``k6-2``
-     ``k6-3``
-     ``athlon``         - ``athlon-tbird``
-     ``athlon-4``       - ``athlon-xp``
-                        - ``athlon-mp``
-     ``k8``             - ``opteron``
-                        - ``athlon64``
-                        - ``athlon-fx``
-     ``k8-sse3``        - ``opteron-sse3``
-                        - ``athlon64-sse3``
-     ``amdfam10h``      - ``barcelona``
-     ``btver1``
-     ``btver2``
-     ``bdver1``
-     ``bdver2``
-     ``bdver3``
-     ``bdver4``
-     ``znver1``
-     ``geode``
-     ``winchip-c6``
-     ``winchip2``
-     ``c3``
-     ``c3-2``
-     ================== ===================

llvm/docs/index.rst

@@ -276,7 +276,6 @@ For API clients and LLVM developers.
    HowToUseAttributes
    NVPTXUsage
    AMDGPUUsage
-   X86Usage
    StackMaps
    InAlloca
    BigEndianNEON
@@ -381,9 +380,6 @@ For API clients and LLVM developers.
 :doc:`AMDGPUUsage`
    This document describes using the AMDGPU backend to compile GPU kernels.
 
-:doc:`X86Usage`
-   This document describes using the X86 backend.
-
 :doc:`StackMaps`
   LLVM support for mapping instruction addresses to the location of
   values and allowing code to be patched.