forked from OSchip/llvm-project
Fix va_arg to generate LDDFi for floating point values, instead of LDXi.
All non-FP cases use LDXi as before. llvm-svn: 7765
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@ -2807,13 +2807,15 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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case 64: // reg: Phi(reg,reg)
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case 64: // reg: Phi(reg,reg)
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break; // don't forward the value
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break; // don't forward the value
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case 65: // reg: VaArg(reg)
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case 65: // reg: VaArg(reg): the va_arg instruction
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{
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{
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// Use value initialized by va_start as pointer to args on the stack.
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// Use value initialized by va_start as pointer to args on the stack.
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// Load argument via current pointer value, then increment pointer.
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// Load argument via current pointer value, then increment pointer.
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int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
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int argSize = target.getFrameInfo().getSizeOfEachArgOnStack();
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Instruction* vaArgI = subtreeRoot->getInstruction();
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Instruction* vaArgI = subtreeRoot->getInstruction();
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mvec.push_back(BuildMI(V9::LDXi, 3).addReg(vaArgI->getOperand(0)).
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MachineOpCode loadOp = vaArgI->getType()->isFloatingPoint()? V9::LDDFi
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: V9::LDXi;
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mvec.push_back(BuildMI(loadOp, 3).addReg(vaArgI->getOperand(0)).
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addSImm(0).addRegDef(vaArgI));
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addSImm(0).addRegDef(vaArgI));
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mvec.push_back(BuildMI(V9::ADDi, 3).addReg(vaArgI->getOperand(0)).
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mvec.push_back(BuildMI(V9::ADDi, 3).addReg(vaArgI->getOperand(0)).
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addSImm(argSize).addRegDef(vaArgI->getOperand(0)));
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addSImm(argSize).addRegDef(vaArgI->getOperand(0)));
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