From 028efac2d7c2a32c35a093e53ea12f527edff7c7 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper@sifive.com>
Date: Tue, 15 Dec 2020 13:34:04 -0800
Subject: [PATCH] [RISCV] Only custom legalize i32 arguments to vector
 intrinsics on RV64.

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 529a5bf784f4..c0202e3f19e0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -340,9 +340,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   if (Subtarget.hasStdExtV()) {
     setBooleanVectorContents(ZeroOrOneBooleanContent);
+
     // RVV intrinsics may have illegal operands.
-    for (auto VT : {MVT::i8, MVT::i16, MVT::i32})
-      setOperationAction(ISD::INTRINSIC_WO_CHAIN, VT, Custom);
+    setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i8, Custom);
+    setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i16, Custom);
+    if (Subtarget.is64Bit())
+      setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i32, Custom);
   }
 
   // Function alignments.