forked from OSchip/llvm-project
[X86] The TEST instruction is eliminated when BSF/TZCNT is used
Summary: These changes cover the PR#31399. Now the ffs(x) function is lowered to (x != 0) ? llvm.cttz(x) + 1 : 0 and it corresponds to the following llvm code: %cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true) %tobool = icmp eq i32 %v, 0 %.op = add nuw nsw i32 %cnt, 1 %add = select i1 %tobool, i32 0, i32 %.op and x86 asm code: bsfl %edi, %ecx addl $1, %ecx testl %edi, %edi movl $0, %eax cmovnel %ecx, %eax In this case the 'test' instruction can't be eliminated because the 'add' instruction modifies the EFLAGS, namely, ZF flag that is set by the 'bsf' instruction when 'x' is zero. We now produce the following code: bsfl %edi, %ecx movl $-1, %eax cmovnel %ecx, %eax addl $1, %eax Patch by Ivan Kulagin Reviewers: davide, craig.topper, spatel, RKSimon Reviewed By: craig.topper Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D48765 llvm-svn: 336768
This commit is contained in:
Craig Topper
parent
709f773a88
commit
02867f0fa3
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@ -33452,6 +33452,36 @@ static SDValue combineCMov(SDNode *N, SelectionDAG &DAG,
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}
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}
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}
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}
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// Handle (CMOV (ADD (CTTZ X), C), C-1, (X != 0)) ->
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// (ADD (CMOV (CTTZ X), -1, (X != 0)), C) or
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// (CMOV C-1, (ADD (CTTZ X), C), (X == 0)) ->
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// (ADD (CMOV C-1, (CTTZ X), (X == 0)), C)
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if (CC == X86::COND_NE || CC == X86::COND_E) {
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auto *Cnst = CC == X86::COND_E ? dyn_cast<ConstantSDNode>(TrueOp)
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: dyn_cast<ConstantSDNode>(FalseOp);
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SDValue Add = CC == X86::COND_E ? FalseOp : TrueOp;
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if (Cnst && Add.getOpcode() == ISD::ADD && Add.hasOneUse()) {
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auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
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SDValue AddOp2 = Add.getOperand(0);
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if (AddOp1 && (AddOp2.getOpcode() == ISD::CTTZ_ZERO_UNDEF ||
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AddOp2.getOpcode() == ISD::CTTZ)) {
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APInt Diff = Cnst->getAPIntValue() - AddOp1->getAPIntValue();
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if (CC == X86::COND_NE) {
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Add = DAG.getNode(X86ISD::CMOV, DL, Add.getValueType(), AddOp2,
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DAG.getConstant(Diff, DL, Add.getValueType()),
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DAG.getConstant(CC, DL, MVT::i8), Cond);
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} else {
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Add = DAG.getNode(X86ISD::CMOV, DL, Add.getValueType(),
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DAG.getConstant(Diff, DL, Add.getValueType()),
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AddOp2, DAG.getConstant(CC, DL, MVT::i8), Cond);
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}
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return DAG.getNode(X86ISD::ADD, DL, Add.getValueType(), Add,
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SDValue(AddOp1, 0));
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}
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}
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}
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return SDValue();
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return SDValue();
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}
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}
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@ -3591,6 +3591,13 @@ static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
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case X86::TZCNT32rr: case X86::TZCNT32rm:
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case X86::TZCNT32rr: case X86::TZCNT32rm:
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case X86::TZCNT64rr: case X86::TZCNT64rm:
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case X86::TZCNT64rr: case X86::TZCNT64rm:
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return X86::COND_B;
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return X86::COND_B;
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case X86::BSF16rr:
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case X86::BSF16rm:
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case X86::BSF32rr:
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case X86::BSF32rm:
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case X86::BSF64rr:
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case X86::BSF64rm:
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return X86::COND_E;
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}
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}
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}
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}
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@ -1,5 +1,6 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -verify-machineinstrs -mattr=+bmi < %s | FileCheck -check-prefix=BMI -enable-var-scope %s
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define i32 @select_and1(i32 %x, i32 %y) {
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define i32 @select_and1(i32 %x, i32 %y) {
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; CHECK-LABEL: select_and1:
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; CHECK-LABEL: select_and1:
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@ -279,3 +280,97 @@ define double @frem_constant_sel_constants(i1 %cond) {
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%bo = frem double 5.1, %sel
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%bo = frem double 5.1, %sel
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ret double %bo
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ret double %bo
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}
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}
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declare i64 @llvm.cttz.i64(i64, i1)
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define i64 @cttz_64_eq_select(i64 %v) nounwind {
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; CHECK-LABEL: cttz_64_eq_select:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bsfq %rdi, %rcx
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; CHECK-NEXT: movq $-1, %rax
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; CHECK-NEXT: cmoveq %rcx, %rax
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; CHECK-NEXT: addq $6, %rax
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; CHECK-NEXT: retq
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; BMI-LABEL: cttz_64_eq_select:
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; BMI: # %bb.0:
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; BMI-NEXT: tzcntq %rdi, %rcx
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; BMI-NEXT: movq $-1, %rax
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; BMI-NEXT: cmovbq %rcx, %rax
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; BMI-NEXT: addq $6, %rax
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; BMI-NEXT: retq
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%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
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%tobool = icmp eq i64 %v, 0
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%.op = add nuw nsw i64 %cnt, 6
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%add = select i1 %tobool, i64 5, i64 %.op
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ret i64 %add
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}
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define i64 @cttz_64_ne_select(i64 %v) nounwind {
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; CHECK-LABEL: cttz_64_ne_select:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bsfq %rdi, %rcx
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; CHECK-NEXT: movq $-1, %rax
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; CHECK-NEXT: cmoveq %rcx, %rax
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; CHECK-NEXT: addq $6, %rax
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; CHECK-NEXT: retq
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; BMI-LABEL: cttz_64_ne_select:
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; BMI: # %bb.0:
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; BMI-NEXT: tzcntq %rdi, %rcx
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; BMI-NEXT: movq $-1, %rax
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; BMI-NEXT: cmovbq %rcx, %rax
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; BMI-NEXT: addq $6, %rax
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; BMI-NEXT: retq
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%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
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%tobool = icmp ne i64 %v, 0
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%.op = add nuw nsw i64 %cnt, 6
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%add = select i1 %tobool, i64 %.op, i64 5
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ret i64 %add
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}
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declare i32 @llvm.cttz.i32(i32, i1)
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define i32 @cttz_32_eq_select(i32 %v) nounwind {
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; CHECK-LABEL: cttz_32_eq_select:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bsfl %edi, %ecx
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovel %ecx, %eax
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; CHECK-NEXT: addl $6, %eax
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; CHECK-NEXT: retq
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; BMI-LABEL: cttz_32_eq_select:
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; BMI: # %bb.0:
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; BMI-NEXT: tzcntl %edi, %ecx
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; BMI-NEXT: movl $-1, %eax
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; BMI-NEXT: cmovbl %ecx, %eax
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; BMI-NEXT: addl $6, %eax
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; BMI-NEXT: retq
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%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
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%tobool = icmp eq i32 %v, 0
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%.op = add nuw nsw i32 %cnt, 6
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%add = select i1 %tobool, i32 5, i32 %.op
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ret i32 %add
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}
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define i32 @cttz_32_ne_select(i32 %v) nounwind {
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; CHECK-LABEL: cttz_32_ne_select:
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; CHECK: # %bb.0:
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; CHECK-NEXT: bsfl %edi, %ecx
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; CHECK-NEXT: movl $-1, %eax
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; CHECK-NEXT: cmovel %ecx, %eax
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; CHECK-NEXT: addl $6, %eax
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; CHECK-NEXT: retq
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; BMI-LABEL: cttz_32_ne_select:
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; BMI: # %bb.0:
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; BMI-NEXT: tzcntl %edi, %ecx
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; BMI-NEXT: movl $-1, %eax
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; BMI-NEXT: cmovbl %ecx, %eax
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; BMI-NEXT: addl $6, %eax
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; BMI-NEXT: retq
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%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
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%tobool = icmp ne i32 %v, 0
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%.op = add nuw nsw i32 %cnt, 6
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%add = select i1 %tobool, i32 %.op, i32 5
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ret i32 %add
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}
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