forked from OSchip/llvm-project
[OpenMP][AArch64] Fix compile with LLVM trunk.
The code is currently using the ambiguous instruction "sub sp, sp, w9, lsl #4". The ARM reference manual says this isn't valid, and it's not clear whether it's supposed to mean uxtw or uxtx. It doesn't matter which instruction we use here, since the high bits of the operand are zero anyway, so I arbitrarily choose uxtw, to preserve the register name. See https://reviews.llvm.org/D60840 for the LLVM patch. Differential Revision: https://reviews.llvm.org/D61770 llvm-svn: 360711
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openmp/runtime/src
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@ -1243,7 +1243,7 @@ __tid = 8
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orr w9, wzr, #1
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add w9, w9, w3, lsr #1
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sub sp, sp, w9, lsl #4
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sub sp, sp, w9, uxtw #4
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mov x11, sp
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mov x8, x0
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