forked from OSchip/llvm-project
[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance
This patch implement the following instructions: - addpcis subpcis - maddhd maddhdu maddld - modsw moduw modsd modud - darn - extswsli extswsli. - setb - dtstsfi dtstsfiq Total 15 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton http://reviews.llvm.org/D17885 llvm-svn: 265505
This commit is contained in:
Chuang-Yu Cheng
parent
eaf4b3d75c
commit
024a623c55
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@ -530,6 +530,10 @@ public:
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(Kind == Immediate && isInt<16>(getImm()) &&
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(getImm() & 3) == 0); }
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bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
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bool isD8RCRegNumber() const { return Kind == Immediate &&
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isUInt<5>(getImm()) &&
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// required even register id
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!(getImm() & 0x1); }
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bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
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bool isCCRegNumber() const { return (Kind == Expression
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&& isUInt<3>(getExprCRVal())) ||
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@ -592,6 +596,11 @@ public:
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Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
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}
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void addRegD8RCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
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}
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void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
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@ -1222,6 +1231,19 @@ void PPCAsmParser::ProcessInstruction(MCInst &Inst,
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Inst = TmpInst;
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break;
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}
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// ISA3.0 Instructions:
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case PPC::SUBPCIS:
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case PPC::LNIA: {
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MCInst TmpInst;
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TmpInst.setOpcode(PPC::ADDPCIS);
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TmpInst.addOperand(Inst.getOperand(0));
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if (Opcode == PPC::SUBPCIS)
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addNegOperand(TmpInst, Inst.getOperand(1), getContext());
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else
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TmpInst.addOperand(MCOperand::createImm(0));
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Inst = TmpInst;
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break;
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}
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}
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}
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@ -242,6 +242,12 @@ static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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return decodeRegisterClass(Inst, RegNo, FRegs);
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}
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static DecodeStatus DecodeD8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, FRegs);
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}
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static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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@ -1263,6 +1263,63 @@ def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>
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let Predicates = [IsISA3_0] in {
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// [PO RT RA RB RC XO]
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class VA_RT5_RA5_RB5_RC5<bits<6> xo, string opc, InstrItinClass itin,
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list<dag> pattern>
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: VAForm_1a<xo, (outs g8rc:$rD), (ins g8rc:$rA, g8rc:$rB, g8rc:$rC),
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!strconcat(opc, " $rD, $rA, $rB, $rC"), itin, pattern>;
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// 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord
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def MADDHD : VA_RT5_RA5_RB5_RC5<48, "maddhd" , IIC_IntGeneral, []>;
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def MADDHDU : VA_RT5_RA5_RB5_RC5<49, "maddhdu", IIC_IntGeneral, []>;
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def MADDLD : VA_RT5_RA5_RB5_RC5<51, "maddld ", IIC_IntGeneral, []>;
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let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
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// Add PC Immediate Shifted
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def ADDPCIS8 : DX_RD5_IM16<19, 2, (outs g8rc:$rD), (ins s16imm:$IMM),
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"addpcis $rD, $IMM", IIC_IntSimple, []>;
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// Modulo {Signed/Unsigned}-Word
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def MODSW8 : X_RT5_RA5_RB5<779, "modsw", g8rc, IIC_IntDivW, []>;
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def MODUW8 : X_RT5_RA5_RB5<267, "moduw", g8rc, IIC_IntDivW, []>;
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}
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// Modulo {Signed/Unsigned}-DWord
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def MODSD : X_RT5_RA5_RB5<777, "modsd", g8rc, IIC_IntDivW, []>;
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def MODUD : X_RT5_RA5_RB5<265, "modud", g8rc, IIC_IntDivW, []>;
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// [PO RS RA sh XO sh Rc]
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multiclass XS_RS5_RA5_SH5r<bits<6> opcode, bits<9> xo, string opc,
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InstrItinClass itin, list<dag> pattern> {
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let BaseName = opc in {
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def NAME : XSForm_1<opcode, xo, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
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!strconcat(opc, " $rA, $rS, $SH"), itin, pattern>;
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let Defs = [CR0] in
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def o : XSForm_1<opcode, xo, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
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!strconcat(opc, ". $rA, $rS, $SH"), itin, pattern>,
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isDOT;
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}
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}
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// Deliver A Random Number
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def DARN : X_RD5_L2<31, 755, (outs g8rc:$rD), (ins u2imm:$L), "darn $rD, $L",
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IIC_IntGeneral, []>;
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// Extend-Sign Word and Shift Left Immediate
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defm EXTSWSLI : XS_RS5_RA5_SH5r<31, 445, "extswsli" , IIC_IntShift, []>;
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// Set Boolean
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def SETB : X_RD5_BFA3<31, 128, (outs g8rc:$rD), (ins u3imm:$BFA),
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"setb $rD, $BFA", IIC_IntGeneral, []>;
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// DFP Test Significance Immediate [Quad]
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def DTSTSFI : X_BF3_IM6_RS5<59, 675,
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(outs crbitrc:$BF), (ins u6imm:$UIM, f8rc:$FRB),
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"dtstsfi $BF, $UIM, $FRB", IIC_FPGeneral, []>;
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def DTSTSFIQ : X_BF3_IM6_RS5<63, 675,
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(outs crbitrc:$BF), (ins u6imm:$UIM, d8rc:$FRBp),
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"dtstsfiq $BF, $UIM, $FRBp", IIC_FPGeneral, []>;
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class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
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InstrItinClass itin, list<dag> pattern>
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: X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
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@ -376,6 +376,23 @@ class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
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let Inst{29-31} = xo;
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}
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// DX-Form: [PO RT d1 d0 XO d2]
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class DX_RD5_IM16<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<5> RD;
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bits<16> IMM;
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let Pattern = pattern;
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let Inst{6-10} = RD;
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// IMM = d0 || d1 || d2
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let Inst{11-15} = IMM{5-1}; // d1
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let Inst{16-25} = IMM{15-6}; // d0
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let Inst{26-30} = xo;
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let Inst{31} = IMM{0}; // d2
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}
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// 1.7.6 X-Form
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class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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@ -762,6 +779,12 @@ class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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let Inst{31} = RC;
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}
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// [PO RT RA RB XO /]
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class X_RT5_RA5_RB5<bits<10> xo, string opc, RegisterOperand type,
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InstrItinClass itin, list<dag> pattern>
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: XForm_base_r3xo<31, xo, (outs type:$rD), (ins type:$rA, type:$rB),
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!strconcat(opc, " $rD, $rA, $rB"), itin, pattern>;
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// e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
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class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin, list<dag> pattern>
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@ -769,6 +792,57 @@ class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
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let A = xo2;
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}
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// [PO RT /// L /// XO /]
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class X_RD5_L2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<5> RD;
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bits<2> L;
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let Pattern = pattern;
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let Inst{6-10} = RD;
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let Inst{11-13} = 0;
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let Inst{14-15} = L;
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let Inst{16-20} = 0;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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// [PO RT BFA // /// XO /]
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class X_RD5_BFA3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<5> RD;
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bits<3> BFA;
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let Pattern = pattern;
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let Inst{6-10} = RD;
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let Inst{11-13} = BFA;
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let Inst{14-20} = 0;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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// [PO BF / UIM FRB XO /] or [PO BF / UIM FRBp XO /]
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class X_BF3_IM6_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<3> BF;
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bits<6> UIM;
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bits<5> FRB;
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let Pattern = pattern;
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let Inst{6-8} = BF;
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let Inst{9} = 0;
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let Inst{10-15} = UIM;
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let Inst{16-20} = FRB;
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let Inst{21-30} = xo;
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let Inst{31} = 0;
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}
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class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin, list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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@ -423,6 +423,12 @@ def PPCRegF4RCAsmOperand : AsmOperandClass {
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def f4rc : RegisterOperand<F4RC> {
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let ParserMatchClass = PPCRegF4RCAsmOperand;
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}
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def PPCRegD8RCAsmOperand : AsmOperandClass {
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let Name = "RegD8RC"; let PredicateMethod = "isD8RCRegNumber";
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}
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def d8rc : RegisterOperand<D8RC> {
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let ParserMatchClass = PPCRegD8RCAsmOperand;
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}
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def PPCRegVRRCAsmOperand : AsmOperandClass {
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let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
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}
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@ -4188,6 +4194,17 @@ def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
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let Predicates = [IsISA3_0] in {
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// Add PC Immediate Shifted
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def ADDPCIS : DX_RD5_IM16<19, 2, (outs gprc:$rD), (ins s16imm:$IMM),
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"addpcis $rD, $IMM", IIC_IntSimple, []>;
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// Extended Mnemonics of ADDPCIS
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def SUBPCIS : PPCAsmPseudo<"subpcis $rD, $IMM", (ins gprc:$rD, s16imm:$IMM)>;
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def LNIA : PPCAsmPseudo<"lnia $rD", (ins gprc:$rD)>;
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// Modulo {Signed/Unsigned}-Word
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def MODSW : X_RT5_RA5_RB5<779, "modsw", gprc, IIC_IntDivW, []>;
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def MODUW : X_RT5_RA5_RB5<267, "moduw", gprc, IIC_IntDivW, []>;
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// Copy-Paste Facility
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// We prefix 'CP' to COPY due to name conflict in Target.td. We also prefix to
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// PASTE for naming consistency.
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@ -18,6 +18,8 @@ def sub_un : SubRegIndex<1, 3>;
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def sub_32 : SubRegIndex<32>;
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def sub_64 : SubRegIndex<64>;
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def sub_128 : SubRegIndex<128>;
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def subreg_l64 : SubRegIndex<64, 0>;
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def subreg_h64 : SubRegIndex<64, 64>;
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}
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@ -49,6 +51,14 @@ class FPR<bits<5> num, string n> : PPCReg<n> {
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let HWEncoding{4-0} = num;
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}
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// DPR - One of the 16 128 bit floating-point registers
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// It is composed of FPR_even and FPR_odd
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class DPR<FPR even, FPR odd, string n> : PPCReg<n> {
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let HWEncoding = even.HWEncoding;
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let SubRegs = [even, odd];
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let SubRegIndices = [subreg_l64, subreg_h64];
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}
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// QFPR - One of the 32 256-bit floating-point vector registers (used for QPX)
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class QFPR<FPR SubReg, string n> : PPCReg<n> {
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let HWEncoding = SubReg.HWEncoding;
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@ -116,6 +126,13 @@ foreach Index = 0-31 in {
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DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
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}
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// 128-bit Paired Floating-point registers
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foreach Index = 0-15 in {
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def D#Index :
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DPR<!cast<FPR>("F"#!shl(Index, 1)),
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!cast<FPR>("F"#!add(!shl(Index, 1), 1)), "f"#!shl(Index, 1)>;
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}
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// Floating-point vector subregisters (for VSX)
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foreach Index = 0-31 in {
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def VF#Index : VF<Index, "vs" # !add(Index, 32)>;
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@ -288,6 +305,9 @@ def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
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(sequence "F%u", 31, 14))>;
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def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
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def D8RC : RegisterClass<"PPC", [f128], 128, (add (sequence "D%u", 0, 6),
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(sequence "D%u", 15, 7))>;
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def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32], 128,
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(add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
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V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
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@ -575,6 +575,79 @@ Move to CR from XER Extended (mcrxrx):
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- Is there a use for this in LLVM?
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Fixed Point Facility:
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- Add PC Immediate Shifted: addpcis subpcis
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. Thinking to use it on PC relative addressing mode?
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- 64-bit Fixed-Point Multiply-Add Low DWord: maddld
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. SDAG:
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(set i64:$rD, (add (mul $rA, $rB), $rC))
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- 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned: maddhd maddhdu
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. Use intrinsic:
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(set i64:$rD, (int_ppc_maddhd i64:$rA, i64:$rB), i64:$rC))
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(set i64:$rD, (int_ppc_maddhdu i64:$rA, i64:$rB), i64:$rC))
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- Modulo {Signed/Unsigned}-{Word/DWord}: modsw moduw modsd modud
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. Map modulo signed to llvm srem, modulo unsigned to urem because each pair
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has same semantics, as follows:
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llvm srem:
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1. This instruction returns the remainder of a division (where the result is
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either zero or has the same sign as the dividend, op1)
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2. Undefined behavior:
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- <anything> % 0
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- Overflow: e.g. -2147483648 % -1
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In this case, the remainder doesn’t actually overflow, but this rule
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lets srem be implemented using instructions that return both the result
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of the division and the remainder.
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Modulo Signed:
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1. remainder = dividend - (quotient × divisor)
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where
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0 ≤ remainder < |divisor|, if the dividend ≥ 0
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-|divisor| < remainder ≤ 0 , if the dividend < 0
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2. Undefined behavior:
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- <anything> % 0
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- 0x8000_0000 % -1
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. SDAG:
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(set i32:$rD, (srem i32:$rA, i32:$rB)) // modsw
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(set i32:$rD, (urem i32:$rA, i32:$rB)) // moduw
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(set i64:$rD, (srem i64:$rA, i64:$rB)) // modsd
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(set i64:$rD, (urem i64:$rA, i64:$rB)) // modud
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. Note:
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The quotient is not supplied as a result in modulo word (32-bit)
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instructions
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- Deliver A Random Number: darn
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. Intrinsic?
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(set i64:$rD, (int_ppc_darn i2:$L))
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. Thinking for using it on c/c++ rand() implementation
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- Extend-Sign Word and Shift Left Immediate: extswsli extswsli.
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. SDAG:
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(set i64:$rA, shl((sext i32:$rS, i64), i6$SH))
|
||||
|
||||
- Set Boolean: setb
|
||||
. Thinking to use it on:
|
||||
|
||||
if (cond)
|
||||
return true;
|
||||
return false;
|
||||
|
||||
. Need Intrinsic?
|
||||
(set i64:rD, (int_ppc_setb i3:$BFA))
|
||||
|
||||
- DFP Test Significance Immediate [Quad]: dtstsfi dtstsfiq
|
||||
. Need write inline assembly to test paired floating point register
|
||||
allocation for dtstsfiq
|
||||
|
||||
. Intrinsics:
|
||||
(set i1:$BF, (int_ppc_dtstsfi i6:$UIM, f64:$FRB))
|
||||
(set i1:$BF, (int_ppc_dtstsfiq i6:$UIM, f128:$FRBp))
|
||||
|
||||
- Copy-Paste Facility: copy copy_first cp_abort paste paste. paste_last
|
||||
. Use instrinstics:
|
||||
|
|
|
|||
|
|
@ -670,6 +670,50 @@
|
|||
# CHECK: mfsrin 10, 12
|
||||
0x7d 0x40 0x65 0x26
|
||||
|
||||
# ISA3.0 Instructions:
|
||||
|
||||
# CHECK: addpcis 1, -12345
|
||||
0x4c 0x23 0xcf 0xc5
|
||||
|
||||
# CHECK: maddhd 30, 27, 7, 2
|
||||
0x13 0xdb 0x38 0xb0
|
||||
|
||||
# CHECK: maddhdu 15, 12, 1, 3
|
||||
0x11 0xec 0x08 0xf1
|
||||
|
||||
# CHECK: maddld 13, 10, 6, 4
|
||||
0x11 0xaa 0x31 0x33
|
||||
|
||||
# CHECK: modsw 2, 3, 4
|
||||
0x7c 0x43 0x26 0x16
|
||||
|
||||
# CHECK: moduw 3, 7, 5
|
||||
0x7c 0x67 0x2a 0x16
|
||||
|
||||
# CHECK: modsd 10, 13, 14
|
||||
0x7d 0x4d 0x76 0x12
|
||||
|
||||
# CHECK: modud 21, 15, 27
|
||||
0x7e 0xaf 0xda 0x12
|
||||
|
||||
# CHECK: darn 31, 2
|
||||
0x7f 0xe2 0x05 0xe6
|
||||
|
||||
# CHECK: extswsli 15, 18, 63
|
||||
0x7e 0x4f 0xfe 0xf6
|
||||
|
||||
# CHECK: extswsli. 11, 27, 31
|
||||
0x7f 0x6b 0xfe 0xf5
|
||||
|
||||
# CHECK: setb 2, 7
|
||||
0x7c 0x5c 0x01 0x00
|
||||
|
||||
# CHECK: dtstsfi 7, 63, 1
|
||||
0xef 0xbf 0x0d 0x46
|
||||
|
||||
# CHECK: dtstsfiq 4, 63, 4
|
||||
0xfe 0x3f 0x25 0x46
|
||||
|
||||
# CHECK: copy 2, 19, 1
|
||||
0x7c 0x22 0x9e 0x0c
|
||||
|
||||
|
|
|
|||
|
|
@ -3666,6 +3666,15 @@
|
|||
# CHECK-LE: attn # encoding: [0x00,0x02,0x00,0x00]
|
||||
attn
|
||||
|
||||
# ISA3.0 Instructions:
|
||||
# Extended Mnemonics of ADDPCIS
|
||||
# CHECK-BE: addpcis 1, -12345 # encoding: [0x4c,0x23,0xcf,0xc5]
|
||||
# CHECK-LE: addpcis 1, -12345 # encoding: [0xc5,0xcf,0x23,0x4c]
|
||||
subpcis 1, 12345
|
||||
# CHECK-BE: addpcis 12, 0 # encoding: [0x4d,0x80,0x00,0x04]
|
||||
# CHECK-LE: addpcis 12, 0 # encoding: [0x04,0x00,0x80,0x4d]
|
||||
lnia 12
|
||||
|
||||
# Copy-Paste Facility (Extended Mnemonics):
|
||||
# CHECK-BE: copy 2, 19, 0 # encoding: [0x7c,0x02,0x9e,0x0c]
|
||||
# CHECK-LE: copy 2, 19, 0 # encoding: [0x0c,0x9e,0x02,0x7c]
|
||||
|
|
|
|||
|
|
@ -855,6 +855,64 @@
|
|||
# CHECK-LE: mfsrin 10, 12 # encoding: [0x26,0x65,0x40,0x7d]
|
||||
mfsrin %r10,%r12
|
||||
|
||||
# ISA3.0 Instructions:
|
||||
|
||||
# Add PC Immediate Shifted
|
||||
# CHECK-BE: addpcis 1, -12345 # encoding: [0x4c,0x23,0xcf,0xc5]
|
||||
# CHECK-LE: addpcis 1, -12345 # encoding: [0xc5,0xcf,0x23,0x4c]
|
||||
addpcis 1, -12345
|
||||
|
||||
# 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord
|
||||
# CHECK-BE: maddhd 30, 27, 7, 2 # encoding: [0x13,0xdb,0x38,0xb0]
|
||||
# CHECK-LE: maddhd 30, 27, 7, 2 # encoding: [0xb0,0x38,0xdb,0x13]
|
||||
maddhd 30, 27, 7, 2
|
||||
# CHECK-BE: maddhdu 15, 12, 1, 3 # encoding: [0x11,0xec,0x08,0xf1]
|
||||
# CHECK-LE: maddhdu 15, 12, 1, 3 # encoding: [0xf1,0x08,0xec,0x11]
|
||||
maddhdu 15, 12, 1, 3
|
||||
# CHECK-BE: maddld 13, 10, 6, 4 # encoding: [0x11,0xaa,0x31,0x33]
|
||||
# CHECK-LE: maddld 13, 10, 6, 4 # encoding: [0x33,0x31,0xaa,0x11]
|
||||
maddld 13, 10, 6, 4
|
||||
|
||||
# Modulo {Signed/Unsigned}-{Word/DWord}
|
||||
# CHECK-BE: modsw 2, 3, 4 # encoding: [0x7c,0x43,0x26,0x16]
|
||||
# CHECK-LE: modsw 2, 3, 4 # encoding: [0x16,0x26,0x43,0x7c]
|
||||
modsw 2, 3, 4
|
||||
# CHECK-BE: moduw 3, 7, 5 # encoding: [0x7c,0x67,0x2a,0x16]
|
||||
# CHECK-LE: moduw 3, 7, 5 # encoding: [0x16,0x2a,0x67,0x7c]
|
||||
moduw 3, 7, 5
|
||||
# CHECK-BE: modsd 10, 13, 14 # encoding: [0x7d,0x4d,0x76,0x12]
|
||||
# CHECK-LE: modsd 10, 13, 14 # encoding: [0x12,0x76,0x4d,0x7d]
|
||||
modsd 10, 13, 14
|
||||
# CHECK-BE: modud 21, 15, 27 # encoding: [0x7e,0xaf,0xda,0x12]
|
||||
# CHECK-LE: modud 21, 15, 27 # encoding: [0x12,0xda,0xaf,0x7e]
|
||||
modud 21, 15, 27
|
||||
|
||||
# Deliver A Random Number
|
||||
# CHECK-BE: darn 31, 2 # encoding: [0x7f,0xe2,0x05,0xe6]
|
||||
# CHECK-LE: darn 31, 2 # encoding: [0xe6,0x05,0xe2,0x7f]
|
||||
darn 31, 2
|
||||
|
||||
# Extend-Sign Word and Shift Left Immediate
|
||||
# CHECK-BE: extswsli 15, 18, 63 # encoding: [0x7e,0x4f,0xfe,0xf6]
|
||||
# CHECK-LE: extswsli 15, 18, 63 # encoding: [0xf6,0xfe,0x4f,0x7e]
|
||||
extswsli 15, 18, 63
|
||||
# CHECK-BE: extswsli. 11, 27, 31 # encoding: [0x7f,0x6b,0xfe,0xf5]
|
||||
# CHECK-LE: extswsli. 11, 27, 31 # encoding: [0xf5,0xfe,0x6b,0x7f]
|
||||
extswsli. 11, 27, 31
|
||||
|
||||
# Set Boolean
|
||||
# CHECK-BE: setb 2, 7 # encoding: [0x7c,0x5c,0x01,0x00]
|
||||
# CHECK-LE: setb 2, 7 # encoding: [0x00,0x01,0x5c,0x7c]
|
||||
setb 2, 7
|
||||
|
||||
# DFP Test Significance Immediate [Quad]
|
||||
# CHECK-BE: dtstsfi 7, 63, 1 # encoding: [0xef,0xbf,0x0d,0x46]
|
||||
# CHECK-LE: dtstsfi 7, 63, 1 # encoding: [0x46,0x0d,0xbf,0xef]
|
||||
dtstsfi 7, 63, 1
|
||||
# CHECK-BE: dtstsfiq 4, 63, 4 # encoding: [0xfe,0x3f,0x25,0x46]
|
||||
# CHECK-LE: dtstsfiq 4, 63, 4 # encoding: [0x46,0x25,0x3f,0xfe]
|
||||
dtstsfiq 4, 63, 4
|
||||
|
||||
# Copy-Paste Facility
|
||||
# CHECK-BE: copy 2, 19, 1 # encoding: [0x7c,0x22,0x9e,0x0c]
|
||||
# CHECK-LE: copy 2, 19, 1 # encoding: [0x0c,0x9e,0x22,0x7c]
|
||||
|
|
|
|||
Loading…
Reference in New Issue