forked from OSchip/llvm-project
AMDGPU: Add function for getting instruction size
llvm-svn: 271936
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3b2e2a59e8
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02458c2d27
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@ -3116,6 +3116,55 @@ bool SIInstrInfo::isHighLatencyInstruction(const MachineInstr *MI) const {
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return isMUBUF(Opc) || isMTBUF(Opc) || isMIMG(Opc);
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}
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unsigned SIInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
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unsigned Opc = MI.getOpcode();
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const MCInstrDesc &Desc = getMCOpcodeFromPseudo(Opc);
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unsigned DescSize = Desc.getSize();
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// If we have a definitive size, we can use it. Otherwise we need to inspect
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// the operands to know the size.
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if (DescSize == 8 || DescSize == 4)
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return DescSize;
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assert(DescSize == 0);
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// 4-byte instructions may have a 32-bit literal encoded after them. Check
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// operands that coud ever be literals.
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if (isVALU(MI) || isSALU(MI)) {
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int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
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if (Src0Idx == -1)
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return 4; // No operands.
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if (isLiteralConstant(MI.getOperand(Src0Idx), getOpSize(MI, Src0Idx)))
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return 8;
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int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
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if (Src1Idx == -1)
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return 4;
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if (isLiteralConstant(MI.getOperand(Src1Idx), getOpSize(MI, Src1Idx)))
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return 8;
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return 4;
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}
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switch (Opc) {
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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case TargetOpcode::DBG_VALUE:
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case TargetOpcode::BUNDLE:
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case TargetOpcode::EH_LABEL:
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return 0;
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case TargetOpcode::INLINEASM: {
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const MachineFunction *MF = MI.getParent()->getParent();
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const char *AsmStr = MI.getOperand(0).getSymbolName();
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return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
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}
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default:
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llvm_unreachable("unable to find instruction size");
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}
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}
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ArrayRef<std::pair<int, const char *>>
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SIInstrInfo::getSerializableTargetIndices() const {
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static const std::pair<int, const char *> TargetIndices[] = {
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@ -512,6 +512,8 @@ public:
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return get(pseudoToMCOpcode(Opcode));
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}
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unsigned getInstSizeInBytes(const MachineInstr &MI) const;
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ArrayRef<std::pair<int, const char *>>
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getSerializableTargetIndices() const override;
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