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[X86] Tidied up 256-bit -> 2 x 128-bit vector shift extraction. 

lowerShift was manually splitting BUILD_VECTOR cases when it could just call Extract128BitVector which does this anyway.

llvm-svn: 262633
This commit is contained in:
Simon Pilgrim 2016-03-03 17:54:35 +00:00
parent 3fb319c3cf
commit 022afe2538
1 changed files with 2 additions and 14 deletions
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16
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -19781,20 +19781,8 @@ static SDValue LowerShift(SDValue Op, const X86Subtarget &Subtarget,
SDValue V2 = Extract128BitVector(R, NumElems/2, DAG, dl);
// Recreate the shift amount vectors
SDValue Amt1, Amt2;
if (Amt.getOpcode() == ISD::BUILD_VECTOR) {
// Constant shift amount
SmallVector<SDValue, 8> Ops(Amt->op_begin(), Amt->op_begin() + NumElems);
ArrayRef<SDValue> Amt1Csts = makeArrayRef(Ops).slice(0, NumElems / 2);
ArrayRef<SDValue> Amt2Csts = makeArrayRef(Ops).slice(NumElems / 2);
Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt1Csts);
Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Amt2Csts);
} else {
// Variable shift amount
Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
}
SDValue Amt1 = Extract128BitVector(Amt, 0, DAG, dl);
SDValue Amt2 = Extract128BitVector(Amt, NumElems/2, DAG, dl);
// Issue new vector shifts for the smaller types
V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1);