forked from OSchip/llvm-project
[x86] auto-generate complete checks; NFC
llvm-svn: 306114
This commit is contained in:
Sanjay Patel
parent
02469b63c2
commit
021f32fd0f
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@ -1,4 +1,5 @@
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; RUN: llc -mtriple=x86_64-apple-macosx < %s | FileCheck %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s
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; rdar://7610418
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%ptr = type { i8* }
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@ -7,26 +8,30 @@
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%struct.s3 = type { %struct.s3*, %struct.s3*, i32, i32, i32 }
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define fastcc i8* @t(i32 %base) nounwind {
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entry:
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; CHECK-LABEL: t:
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; CHECK: leaq (%rax,%rax,4)
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shlq $9, %rax
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; CHECK-NEXT: leaq (%rax,%rax,4), %rdi
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB0_2
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; CHECK-NEXT: # BB#1: # %bb1
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; CHECK-NEXT: callq bar
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; CHECK-NEXT: .LBB0_2: # %bb2
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; CHECK-NEXT: callq foo
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entry:
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%0 = zext i32 %base to i64
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%1 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0
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br i1 undef, label %bb1, label %bb2
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bb1:
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; CHECK: %bb1
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; CHECK-NOT: shlq $9
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; CHECK-NOT: leaq
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; CHECK: call
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%2 = getelementptr inbounds %struct.s2, %struct.s2* null, i64 %0, i32 0
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call void @bar(i32* %2) nounwind
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unreachable
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bb2:
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; CHECK: %bb2
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; CHECK-NOT: leaq
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; CHECK: callq
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%3 = call fastcc i8* @foo(%struct.s2* %1) nounwind
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unreachable
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@ -44,6 +49,30 @@ declare void @printf(...) nounwind
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define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
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; CHECK-LABEL: commute:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: # kill: %ESI<def> %ESI<kill> %RSI<def>
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; CHECK-NEXT: leal -1(%rdi), %eax
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; CHECK-NEXT: cmpl $2, %eax
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; CHECK-NEXT: ja .LBB1_4
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; CHECK-NEXT: # BB#1: # %sw.bb
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: testb %al, %al
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; CHECK-NEXT: jne .LBB1_4
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; CHECK-NEXT: # BB#2: # %if.end34
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: imull %edi, %esi
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; CHECK-NEXT: leal (%rsi,%rsi,2), %esi
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<kill>
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; CHECK-NEXT: callq printf
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; CHECK-NEXT: addq $8, %rsp
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB1_3: # %for.body53.us
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: jmp .LBB1_3
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; CHECK-NEXT: .LBB1_4: # %sw.bb307
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; CHECK-NEXT: retq
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entry:
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switch i32 %test_case, label %sw.bb307 [
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i32 1, label %sw.bb
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@ -51,67 +80,78 @@ entry:
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i32 3, label %sw.bb
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]
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sw.bb: ; preds = %entry, %entry, %entry
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; CHECK: %sw.bb
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; CHECK-NOT: imull
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sw.bb:
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%mul = mul nsw i32 %test_case, 3
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%mul20 = mul nsw i32 %mul, %scale
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br i1 undef, label %if.end34, label %sw.bb307
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if.end34: ; preds = %sw.bb
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; CHECK: %if.end34
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; CHECK: imull
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; CHECK: leal
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if.end34:
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tail call void (...) @printf(i32 %test_case, i32 %mul20) nounwind
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%tmp = mul i32 %scale, %test_case
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%tmp752 = mul i32 %tmp, 3
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%tmp753 = zext i32 %tmp752 to i64
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br label %bb.nph743.us
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for.body53.us: ; preds = %bb.nph743.us, %for.body53.us
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for.body53.us:
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%exitcond = icmp eq i64 undef, %tmp753
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br i1 %exitcond, label %bb.nph743.us, label %for.body53.us
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bb.nph743.us: ; preds = %for.body53.us, %if.end34
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bb.nph743.us:
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br label %for.body53.us
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sw.bb307: ; preds = %sw.bb, %entry
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sw.bb307:
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ret void
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}
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; CSE physical register defining instruction across MBB boundary.
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; rdar://10660865
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define i32 @cross_mbb_phys_cse(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK-LABEL: cross_mbb_phys_cse:
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; CHECK: cmpl
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; CHECK: ja
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: cmpl %esi, %edi
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; CHECK-NEXT: ja .LBB2_2
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; CHECK-NEXT: # BB#1: # %if.end
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; CHECK-NEXT: sbbl %eax, %eax
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; CHECK-NEXT: .LBB2_2: # %return
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; CHECK-NEXT: retq
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entry:
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%cmp = icmp ugt i32 %a, %b
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br i1 %cmp, label %return, label %if.end
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if.end: ; preds = %entry
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; CHECK-NOT: cmpl
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; CHECK: sbbl
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if.end:
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%cmp1 = icmp ult i32 %a, %b
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%. = sext i1 %cmp1 to i32
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br label %return
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return: ; preds = %if.end, %entry
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return:
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%retval.0 = phi i32 [ 1, %entry ], [ %., %if.end ]
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ret i32 %retval.0
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}
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; rdar://11393714
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define i8* @bsd_memchr(i8* %s, i32 %a, i32 %c, i64 %n) nounwind ssp {
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; CHECK: %entry
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; CHECK-NOT: xorl
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; CHECK: %preheader
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; CHECK-NOT: xorl
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; CHECK: %do.body
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; CHECK-NOT: xorl
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; CHECK: %do.cond
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; CHECK: xorl
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; CHECK: %return
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; CHECK-LABEL: bsd_memchr:
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; CHECK: # BB#0: # %entry
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; CHECK-NEXT: testq %rcx, %rcx
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; CHECK-NEXT: je .LBB3_4
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; CHECK-NEXT: # BB#1: # %preheader
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; CHECK-NEXT: movzbl %dl, %eax
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB3_2: # %do.body
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: cmpl %eax, %esi
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; CHECK-NEXT: je .LBB3_5
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; CHECK-NEXT: # BB#3: # %do.cond
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; CHECK-NEXT: # in Loop: Header=BB3_2 Depth=1
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; CHECK-NEXT: incq %rdi
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; CHECK-NEXT: decq %rcx
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; CHECK-NEXT: jne .LBB3_2
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; CHECK-NEXT: .LBB3_4:
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; CHECK-NEXT: xorl %edi, %edi
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; CHECK-NEXT: .LBB3_5: # %return
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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entry:
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%cmp = icmp eq i64 %n, 0
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br i1 %cmp, label %return, label %preheader
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@ -142,7 +182,22 @@ return:
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declare i1 @t2_func()
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define i32 @t2() {
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define i32 @t2() nounwind {
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; CHECK-LABEL: t2:
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; CHECK: # BB#0:
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; CHECK-NEXT: pushq %rax
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; CHECK-NEXT: movl $42, {{.*}}(%rip)
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; CHECK-NEXT: callq t2_func
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; CHECK-NEXT: testb $1, %al
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; CHECK-NEXT: je .LBB4_2
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; CHECK-NEXT: # BB#1: # %a
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; CHECK-NEXT: movl {{.*}}(%rip), %eax
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: retq
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; CHECK-NEXT: .LBB4_2: # %b
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: popq %rcx
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; CHECK-NEXT: retq
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store i32 42, i32* @t2_global
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%c = call i1 @t2_func()
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br i1 %c, label %a, label %b
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@ -153,8 +208,5 @@ a:
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b:
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ret i32 0
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; CHECK-LABEL: t2:
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; CHECK: t2_global@GOTPCREL(%rip)
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; CHECK-NOT: t2_global@GOTPCREL(%rip)
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}
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