forked from OSchip/llvm-project
[llvm-mca] Remove flag -max-retire-per-cycle, and update the docs.
This is done in preparation for D45259. With D45259, models can specify the size of the reorder buffer, and the retire throughput directly via tablegen. llvm-svn: 329274
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@ -68,11 +68,6 @@ option specifies "``-``", then the output will also be sent to standard output.
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defaults to the 'IssueWidth' specified by the processor scheduling model.
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defaults to the 'IssueWidth' specified by the processor scheduling model.
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If width is zero, then the default dispatch width is used.
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If width is zero, then the default dispatch width is used.
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.. option:: -max-retire-per-cycle=<retire throughput>
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Specify the retire throughput (i.e. how many instructions can be retired by the
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retire control unit every cycle).
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.. option:: -register-file-size=<size>
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.. option:: -register-file-size=<size>
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Specify the size of the register file. When specified, this flag limits
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Specify the size of the register file. When specified, this flag limits
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@ -62,15 +62,15 @@ public:
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Backend(const llvm::MCSubtargetInfo &Subtarget,
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Backend(const llvm::MCSubtargetInfo &Subtarget,
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const llvm::MCRegisterInfo &MRI, InstrBuilder &B, SourceMgr &Source,
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const llvm::MCRegisterInfo &MRI, InstrBuilder &B, SourceMgr &Source,
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unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
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unsigned DispatchWidth = 0, unsigned RegisterFileSize = 0,
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unsigned MaxRetirePerCycle = 0, unsigned LoadQueueSize = 0,
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unsigned LoadQueueSize = 0, unsigned StoreQueueSize = 0,
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unsigned StoreQueueSize = 0, bool AssumeNoAlias = false)
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bool AssumeNoAlias = false)
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: STI(Subtarget), IB(B),
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: STI(Subtarget), IB(B),
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HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
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HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
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LoadQueueSize, StoreQueueSize,
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LoadQueueSize, StoreQueueSize,
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AssumeNoAlias)),
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AssumeNoAlias)),
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DU(llvm::make_unique<DispatchUnit>(
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DU(llvm::make_unique<DispatchUnit>(
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this, STI, MRI, Subtarget.getSchedModel().MicroOpBufferSize,
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this, STI, MRI, Subtarget.getSchedModel().MicroOpBufferSize,
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RegisterFileSize, MaxRetirePerCycle, DispatchWidth, HWS.get())),
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RegisterFileSize, DispatchWidth, HWS.get())),
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SM(Source), Cycles(0) {
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SM(Source), Cycles(0) {
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HWS->setDispatchUnit(DU.get());
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HWS->setDispatchUnit(DU.get());
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}
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}
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@ -192,9 +192,9 @@ private:
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DispatchUnit *Owner;
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DispatchUnit *Owner;
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public:
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public:
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RetireControlUnit(unsigned NumSlots, unsigned RPC, DispatchUnit *DU)
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RetireControlUnit(unsigned NumSlots, DispatchUnit *DU)
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: NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
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: NextAvailableSlotIdx(0), CurrentInstructionSlotIdx(0),
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AvailableSlots(NumSlots), MaxRetirePerCycle(RPC), Owner(DU) {
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AvailableSlots(NumSlots), MaxRetirePerCycle(0), Owner(DU) {
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assert(NumSlots && "Expected at least one slot!");
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assert(NumSlots && "Expected at least one slot!");
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Queue.resize(NumSlots);
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Queue.resize(NumSlots);
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}
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}
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@ -266,14 +266,13 @@ class DispatchUnit {
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public:
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public:
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DispatchUnit(Backend *B, const llvm::MCSubtargetInfo &STI,
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DispatchUnit(Backend *B, const llvm::MCSubtargetInfo &STI,
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const llvm::MCRegisterInfo &MRI, unsigned MicroOpBufferSize,
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const llvm::MCRegisterInfo &MRI, unsigned MicroOpBufferSize,
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unsigned RegisterFileSize, unsigned MaxRetirePerCycle,
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unsigned RegisterFileSize, unsigned MaxDispatchWidth,
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unsigned MaxDispatchWidth, Scheduler *Sched)
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Scheduler *Sched)
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: DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
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: DispatchWidth(MaxDispatchWidth), AvailableEntries(MaxDispatchWidth),
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CarryOver(0U), SC(Sched),
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CarryOver(0U), SC(Sched),
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RAT(llvm::make_unique<RegisterFile>(STI.getSchedModel(), MRI,
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RAT(llvm::make_unique<RegisterFile>(STI.getSchedModel(), MRI,
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RegisterFileSize)),
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RegisterFileSize)),
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RCU(llvm::make_unique<RetireControlUnit>(MicroOpBufferSize,
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RCU(llvm::make_unique<RetireControlUnit>(MicroOpBufferSize, this)),
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MaxRetirePerCycle, this)),
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Owner(B) {}
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Owner(B) {}
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unsigned getDispatchWidth() const { return DispatchWidth; }
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unsigned getDispatchWidth() const { return DispatchWidth; }
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@ -81,11 +81,6 @@ static cl::opt<unsigned> DispatchWidth(
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cl::desc("Dispatch Width. By default it is set equal to IssueWidth"),
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cl::desc("Dispatch Width. By default it is set equal to IssueWidth"),
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cl::init(0));
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cl::init(0));
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static cl::opt<unsigned> MaxRetirePerCycle(
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"max-retire-per-cycle",
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cl::desc("Maximum number of instructions that can be retired in one cycle"),
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cl::init(0));
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static cl::opt<unsigned>
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static cl::opt<unsigned>
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RegisterFileSize("register-file-size",
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RegisterFileSize("register-file-size",
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cl::desc("Maximum number of temporary registers which can "
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cl::desc("Maximum number of temporary registers which can "
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@ -361,8 +356,8 @@ int main(int argc, char **argv) {
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}
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}
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std::unique_ptr<mca::Backend> B = llvm::make_unique<mca::Backend>(
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std::unique_ptr<mca::Backend> B = llvm::make_unique<mca::Backend>(
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*STI, *MRI, *IB, *S, Width, RegisterFileSize, MaxRetirePerCycle,
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*STI, *MRI, *IB, *S, Width, RegisterFileSize, LoadQueueSize,
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LoadQueueSize, StoreQueueSize, AssumeNoAlias);
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StoreQueueSize, AssumeNoAlias);
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std::unique_ptr<mca::BackendPrinter> Printer =
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std::unique_ptr<mca::BackendPrinter> Printer =
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llvm::make_unique<mca::BackendPrinter>(*B);
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llvm::make_unique<mca::BackendPrinter>(*B);
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