diff --git a/libcxxabi/test/test_demangle.pass.cpp b/libcxxabi/test/test_demangle.pass.cpp
index 8cfe6aecb300..a68ec85615e6 100644
--- a/libcxxabi/test/test_demangle.pass.cpp
+++ b/libcxxabi/test/test_demangle.pass.cpp
@@ -12990,9 +12990,9 @@ const char* cases[][2] =
{"_ZN4llvm3X8621GetCondBranchFromCondENS0_8CondCodeE", "llvm::X86::GetCondBranchFromCond(llvm::X86::CondCode)"},
{"_ZN4llvm3X8626GetOppositeBranchConditionENS0_8CondCodeE", "llvm::X86::GetOppositeBranchCondition(llvm::X86::CondCode)"},
{"_ZNK4llvm12X86InstrInfo24isUnpredicatedTerminatorEPKNS_12MachineInstrE", "llvm::X86InstrInfo::isUnpredicatedTerminator(llvm::MachineInstr const*) const"},
- {"_ZNK4llvm12X86InstrInfo13AnalyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::X86InstrInfo::AnalyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},
- {"_ZNK4llvm12X86InstrInfo12RemoveBranchERNS_17MachineBasicBlockE", "llvm::X86InstrInfo::RemoveBranch(llvm::MachineBasicBlock&) const"},
- {"_ZNK4llvm12X86InstrInfo12InsertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::X86InstrInfo::InsertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},
+ {"_ZNK4llvm12X86InstrInfo13analyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::X86InstrInfo::analyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},
+ {"_ZNK4llvm12X86InstrInfo12removeBranchERNS_17MachineBasicBlockE", "llvm::X86InstrInfo::removeBranch(llvm::MachineBasicBlock&) const"},
+ {"_ZNK4llvm12X86InstrInfo12insertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::X86InstrInfo::insertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},
{"_ZNK4llvm12X86InstrInfo11copyPhysRegERNS_17MachineBasicBlockENS_14ilist_iteratorINS_12MachineInstrEEENS_8DebugLocEjjb", "llvm::X86InstrInfo::copyPhysReg(llvm::MachineBasicBlock&, llvm::ilist_iterator<llvm::MachineInstr>, llvm::DebugLoc, unsigned int, unsigned int, bool) const"},
{"_ZNK4llvm12X86InstrInfo19storeRegToStackSlotERNS_17MachineBasicBlockENS_14ilist_iteratorINS_12MachineInstrEEEjbiPKNS_19TargetRegisterClassEPKNS_18TargetRegisterInfoE", "llvm::X86InstrInfo::storeRegToStackSlot(llvm::MachineBasicBlock&, llvm::ilist_iterator<llvm::MachineInstr>, unsigned int, bool, int, llvm::TargetRegisterClass const*, llvm::TargetRegisterInfo const*) const"},
{"_ZN4llvm17addFrameReferenceERKNS_19MachineInstrBuilderEii", "llvm::addFrameReference(llvm::MachineInstrBuilder const&, int, int)"},
@@ -13545,9 +13545,9 @@ const char* cases[][2] =
{"_ZNK4llvm16ARMBaseInstrInfo28CreateTargetHazardRecognizerEPKNS_13TargetMachineEPKNS_11ScheduleDAGE", "llvm::ARMBaseInstrInfo::CreateTargetHazardRecognizer(llvm::TargetMachine const*, llvm::ScheduleDAG const*) const"},
{"_ZNK4llvm16ARMBaseInstrInfo34CreateTargetPostRAHazardRecognizerEPKNS_18InstrItineraryDataEPKNS_11ScheduleDAGE", "llvm::ARMBaseInstrInfo::CreateTargetPostRAHazardRecognizer(llvm::InstrItineraryData const*, llvm::ScheduleDAG const*) const"},
{"_ZNK4llvm16ARMBaseInstrInfo21convertToThreeAddressERNS_14ilist_iteratorINS_17MachineBasicBlockEEERNS1_INS_12MachineInstrEEEPNS_13LiveVariablesE", "llvm::ARMBaseInstrInfo::convertToThreeAddress(llvm::ilist_iterator<llvm::MachineBasicBlock>&, llvm::ilist_iterator<llvm::MachineInstr>&, llvm::LiveVariables*) const"},
- {"_ZNK4llvm16ARMBaseInstrInfo13AnalyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::ARMBaseInstrInfo::AnalyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},
- {"_ZNK4llvm16ARMBaseInstrInfo12RemoveBranchERNS_17MachineBasicBlockE", "llvm::ARMBaseInstrInfo::RemoveBranch(llvm::MachineBasicBlock&) const"},
- {"_ZNK4llvm16ARMBaseInstrInfo12InsertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::ARMBaseInstrInfo::InsertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},
+ {"_ZNK4llvm16ARMBaseInstrInfo13analyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::ARMBaseInstrInfo::analyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},
+ {"_ZNK4llvm16ARMBaseInstrInfo12removeBranchERNS_17MachineBasicBlockE", "llvm::ARMBaseInstrInfo::removeBranch(llvm::MachineBasicBlock&) const"},
+ {"_ZNK4llvm16ARMBaseInstrInfo12insertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::ARMBaseInstrInfo::insertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},
{"_ZNK4llvm16ARMBaseInstrInfo22ReverseBranchConditionERNS_15SmallVectorImplINS_14MachineOperandEEE", "llvm::ARMBaseInstrInfo::ReverseBranchCondition(llvm::SmallVectorImpl<llvm::MachineOperand>&) const"},
{"_ZNK4llvm16ARMBaseInstrInfo20PredicateInstructionEPNS_12MachineInstrERKNS_15SmallVectorImplINS_14MachineOperandEEE", "llvm::ARMBaseInstrInfo::PredicateInstruction(llvm::MachineInstr*, llvm::SmallVectorImpl<llvm::MachineOperand> const&) const"},
{"_ZN4llvm27getMatchingCondBranchOpcodeEi", "llvm::getMatchingCondBranchOpcode(int)"},
@@ -14257,9 +14257,9 @@ const char* cases[][2] =
{"_ZNK4llvm15TargetInstrInfo19isLoadFromStackSlotEPKNS_12MachineInstrERi", "llvm::TargetInstrInfo::isLoadFromStackSlot(llvm::MachineInstr const*, int&) const"},
{"_ZNK4llvm15TargetInstrInfo18isStoreToStackSlotEPKNS_12MachineInstrERi", "llvm::TargetInstrInfo::isStoreToStackSlot(llvm::MachineInstr const*, int&) const"},
{"_ZNK4llvm15TargetInstrInfo21convertToThreeAddressERNS_14ilist_iteratorINS_17MachineBasicBlockEEERNS1_INS_12MachineInstrEEEPNS_13LiveVariablesE", "llvm::TargetInstrInfo::convertToThreeAddress(llvm::ilist_iterator<llvm::MachineBasicBlock>&, llvm::ilist_iterator<llvm::MachineInstr>&, llvm::LiveVariables*) const"},
- {"_ZNK4llvm15TargetInstrInfo13AnalyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::TargetInstrInfo::AnalyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},
- {"_ZNK4llvm15TargetInstrInfo12RemoveBranchERNS_17MachineBasicBlockE", "llvm::TargetInstrInfo::RemoveBranch(llvm::MachineBasicBlock&) const"},
- {"_ZNK4llvm15TargetInstrInfo12InsertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::TargetInstrInfo::InsertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},
+ {"_ZNK4llvm15TargetInstrInfo13analyzeBranchERNS_17MachineBasicBlockERPS1_S4_RNS_15SmallVectorImplINS_14MachineOperandEEEb", "llvm::TargetInstrInfo::analyzeBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*&, llvm::MachineBasicBlock*&, llvm::SmallVectorImpl<llvm::MachineOperand>&, bool) const"},
+ {"_ZNK4llvm15TargetInstrInfo12removeBranchERNS_17MachineBasicBlockE", "llvm::TargetInstrInfo::removeBranch(llvm::MachineBasicBlock&) const"},
+ {"_ZNK4llvm15TargetInstrInfo12insertBranchERNS_17MachineBasicBlockEPS1_S3_RKNS_15SmallVectorImplINS_14MachineOperandEEENS_8DebugLocE", "llvm::TargetInstrInfo::insertBranch(llvm::MachineBasicBlock&, llvm::MachineBasicBlock*, llvm::MachineBasicBlock*, llvm::SmallVectorImpl<llvm::MachineOperand> const&, llvm::DebugLoc) const"},
{"_ZNK4llvm15TargetInstrInfo19isProfitableToIfCvtERNS_17MachineBasicBlockEjjff", "llvm::TargetInstrInfo::isProfitableToIfCvt(llvm::MachineBasicBlock&, unsigned int, unsigned int, float, float) const"},
{"_ZNK4llvm15TargetInstrInfo19isProfitableToIfCvtERNS_17MachineBasicBlockEjjS2_jjff", "llvm::TargetInstrInfo::isProfitableToIfCvt(llvm::MachineBasicBlock&, unsigned int, unsigned int, llvm::MachineBasicBlock&, unsigned int, unsigned int, float, float) const"},
{"_ZNK4llvm15TargetInstrInfo25isProfitableToDupForIfCvtERNS_17MachineBasicBlockEjff", "llvm::TargetInstrInfo::isProfitableToDupForIfCvt(llvm::MachineBasicBlock&, unsigned int, float, float) const"},
diff --git a/llvm/docs/WritingAnLLVMBackend.rst b/llvm/docs/WritingAnLLVMBackend.rst
index f8ca9563a3ce..c153114db38f 100644
--- a/llvm/docs/WritingAnLLVMBackend.rst
+++ b/llvm/docs/WritingAnLLVMBackend.rst
@@ -1100,21 +1100,21 @@ Branch Folding and If Conversion
--------------------------------
Performance can be improved by combining instructions or by eliminating
-instructions that are never reached. The ``AnalyzeBranch`` method in
+instructions that are never reached. The ``analyzeBranch`` method in
``XXXInstrInfo`` may be implemented to examine conditional instructions and
-remove unnecessary instructions. ``AnalyzeBranch`` looks at the end of a
+remove unnecessary instructions. ``analyzeBranch`` looks at the end of a
machine basic block (MBB) for opportunities for improvement, such as branch
folding and if conversion. The ``BranchFolder`` and ``IfConverter`` machine
function passes (see the source files ``BranchFolding.cpp`` and
-``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``AnalyzeBranch``
+``IfConversion.cpp`` in the ``lib/CodeGen`` directory) call ``analyzeBranch``
to improve the control flow graph that represents the instructions.
-Several implementations of ``AnalyzeBranch`` (for ARM, Alpha, and X86) can be
-examined as models for your own ``AnalyzeBranch`` implementation. Since SPARC
-does not implement a useful ``AnalyzeBranch``, the ARM target implementation is
+Several implementations of ``analyzeBranch`` (for ARM, Alpha, and X86) can be
+examined as models for your own ``analyzeBranch`` implementation. Since SPARC
+does not implement a useful ``analyzeBranch``, the ARM target implementation is
shown below.
-``AnalyzeBranch`` returns a Boolean value and takes four parameters:
+``analyzeBranch`` returns a Boolean value and takes four parameters:
* ``MachineBasicBlock &MBB`` --- The incoming block to be examined.
@@ -1130,12 +1130,12 @@ shown below.
In the simplest case, if a block ends without a branch, then it falls through
to the successor block. No destination blocks are specified for either ``TBB``
or ``FBB``, so both parameters return ``NULL``. The start of the
-``AnalyzeBranch`` (see code below for the ARM target) shows the function
+``analyzeBranch`` (see code below for the ARM target) shows the function
parameters and the code for the simplest case.
.. code-block:: c++
- bool ARMInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
+ bool ARMInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
std::vector<MachineOperand> &Cond) const
@@ -1145,7 +1145,7 @@ parameters and the code for the simplest case.
return false;
If a block ends with a single unconditional branch instruction, then
-``AnalyzeBranch`` (shown below) should return the destination of that branch in
+``analyzeBranch`` (shown below) should return the destination of that branch in
the ``TBB`` parameter.
.. code-block:: c++
@@ -1171,7 +1171,7 @@ instruction and return the penultimate branch in the ``TBB`` parameter.
A block may end with a single conditional branch instruction that falls through
to successor block if the condition evaluates to false. In that case,
-``AnalyzeBranch`` (shown below) should return the destination of that
+``analyzeBranch`` (shown below) should return the destination of that
conditional branch in the ``TBB`` parameter and a list of operands in the
``Cond`` parameter to evaluate the condition.
@@ -1186,7 +1186,7 @@ conditional branch in the ``TBB`` parameter and a list of operands in the
}
If a block ends with both a conditional branch and an ensuing unconditional
-branch, then ``AnalyzeBranch`` (shown below) should return the conditional
+branch, then ``analyzeBranch`` (shown below) should return the conditional
branch destination (assuming it corresponds to a conditional evaluation of
"``true``") in the ``TBB`` parameter and the unconditional branch destination
in the ``FBB`` (corresponding to a conditional evaluation of "``false``"). A
@@ -1209,14 +1209,14 @@ parameter.
For the last two cases (ending with a single conditional branch or ending with
one conditional and one unconditional branch), the operands returned in the
``Cond`` parameter can be passed to methods of other instructions to create new
-branches or perform other operations. An implementation of ``AnalyzeBranch``
-requires the helper methods ``RemoveBranch`` and ``InsertBranch`` to manage
+branches or perform other operations. An implementation of ``analyzeBranch``
+requires the helper methods ``removeBranch`` and ``insertBranch`` to manage
subsequent operations.
-``AnalyzeBranch`` should return false indicating success in most circumstances.
-``AnalyzeBranch`` should only return true when the method is stumped about what
+``analyzeBranch`` should return false indicating success in most circumstances.
+``analyzeBranch`` should only return true when the method is stumped about what
to do, for example, if a block has three terminating branches.
-``AnalyzeBranch`` may return true if it encounters a terminator it cannot
+``analyzeBranch`` may return true if it encounters a terminator it cannot
handle, such as an indirect branch.
.. _instruction-selector:
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 6d4ab3b2a2a5..8c4d16419fa2 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -701,7 +701,7 @@ public:
/// Returns true if this is a conditional, unconditional, or indirect branch.
/// Predicates below can be used to discriminate between
- /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
+ /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
/// get more information.
bool isBranch(QueryType Type = AnyInBundle) const {
return hasProperty(MCID::Branch, Type);
@@ -715,7 +715,7 @@ public:
/// Return true if this is a branch which may fall
/// through to the next instruction or may transfer control flow to some other
- /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
+ /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
/// information about this branch.
bool isConditionalBranch(QueryType Type = AnyInBundle) const {
return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type);
@@ -723,7 +723,7 @@ public:
/// Return true if this is a branch which always
/// transfers control flow to some other block. The
- /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
+ /// TargetInstrInfo::analyzeBranch method can be used to get more information
/// about this branch.
bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type);
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index ec3c0a0194f6..536fd2489092 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -644,7 +644,7 @@ public:
}
/// Remove the branching code at the end of the specific MBB.
- /// This is only invoked in cases where AnalyzeBranch returns success. It
+ /// This is only invoked in cases where analyzeBranch returns success. It
/// returns the number of instructions that were removed.
/// If \p BytesRemoved is non-null, report the change in code size from the
/// removed instructions.
@@ -654,13 +654,13 @@ public:
}
/// Insert branch code into the end of the specified MachineBasicBlock. The
- /// operands to this method are the same as those returned by AnalyzeBranch.
- /// This is only invoked in cases where AnalyzeBranch returns success. It
+ /// operands to this method are the same as those returned by analyzeBranch.
+ /// This is only invoked in cases where analyzeBranch returns success. It
/// returns the number of instructions inserted. If \p BytesAdded is non-null,
/// report the change in code size from the added instructions.
///
/// It is also invoked by tail merging to add unconditional branches in
- /// cases where AnalyzeBranch doesn't apply because there was no original
+ /// cases where analyzeBranch doesn't apply because there was no original
/// branch to analyze. At least this much must be implemented, else tail
/// merging needs to be disabled.
///
@@ -837,7 +837,7 @@ public:
/// Some x86 implementations have 2-cycle cmov instructions.
///
/// @param MBB Block where select instruction would be inserted.
- /// @param Cond Condition returned by AnalyzeBranch.
+ /// @param Cond Condition returned by analyzeBranch.
/// @param TrueReg Virtual register to select when Cond is true.
/// @param FalseReg Virtual register to select when Cond is false.
/// @param CondCycles Latency from Cond+Branch to select output.
@@ -854,7 +854,7 @@ public:
/// DstReg when Cond is true, and FalseReg to DstReg when Cond is false.
///
/// This function can only be called after canInsertSelect() returned true.
- /// The condition in Cond comes from AnalyzeBranch, and it can be assumed
+ /// The condition in Cond comes from analyzeBranch, and it can be assumed
/// that the same flags or registers required by Cond are available at the
/// insertion point.
///
@@ -862,7 +862,7 @@ public:
/// @param I Insertion point.
/// @param DL Source location for debugging.
/// @param DstReg Virtual register to be defined by select instruction.
- /// @param Cond Condition as computed by AnalyzeBranch.
+ /// @param Cond Condition as computed by analyzeBranch.
/// @param TrueReg Virtual register to copy when Cond is true.
/// @param FalseReg Virtual register to copy when Cons is false.
virtual void insertSelect(MachineBasicBlock &MBB,
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 506f2c09304c..29175af7eb09 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -300,7 +300,7 @@ public:
/// Returns true if this is a conditional, unconditional, or
/// indirect branch. Predicates below can be used to discriminate between
- /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
+ /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to
/// get more information.
bool isBranch() const { return Flags & (1ULL << MCID::Branch); }
@@ -310,7 +310,7 @@ public:
/// Return true if this is a branch which may fall
/// through to the next instruction or may transfer control flow to some other
- /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
+ /// block. The TargetInstrInfo::analyzeBranch method can be used to get more
/// information about this branch.
bool isConditionalBranch() const {
return isBranch() && !isBarrier() && !isIndirectBranch();
@@ -318,7 +318,7 @@ public:
/// Return true if this is a branch which always
/// transfers control flow to some other block. The
- /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
+ /// TargetInstrInfo::analyzeBranch method can be used to get more information
/// about this branch.
bool isUnconditionalBranch() const {
return isBranch() && isBarrier() && !isIndirectBranch();
diff --git a/llvm/lib/CodeGen/BranchFolding.cpp b/llvm/lib/CodeGen/BranchFolding.cpp
index 4b9c50aeb1d3..a38c4f3d74b2 100644
--- a/llvm/lib/CodeGen/BranchFolding.cpp
+++ b/llvm/lib/CodeGen/BranchFolding.cpp
@@ -1437,7 +1437,7 @@ ReoptimizeBlock:
// has been used, but it can happen if tail merging splits a fall-through
// predecessor of a block.
// This has to check PrevBB->succ_size() because EH edges are ignored by
- // AnalyzeBranch.
+ // analyzeBranch.
if (PriorCond.empty() && !PriorTBB && MBB->pred_size() == 1 &&
PrevBB.succ_size() == 1 &&
!MBB->hasAddressTaken() && !MBB->isEHPad()) {
diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index d45e424184d7..fc31a9449e72 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -91,10 +91,10 @@ public:
/// The block containing phis after the if-then-else.
MachineBasicBlock *Tail;
- /// The 'true' conditional block as determined by AnalyzeBranch.
+ /// The 'true' conditional block as determined by analyzeBranch.
MachineBasicBlock *TBB;
- /// The 'false' conditional block as determined by AnalyzeBranch.
+ /// The 'false' conditional block as determined by analyzeBranch.
MachineBasicBlock *FBB;
/// isTriangle - When there is no 'else' block, either TBB or FBB will be
@@ -121,7 +121,7 @@ public:
SmallVector<PHIInfo, 8> PHIs;
private:
- /// The branch condition determined by AnalyzeBranch.
+ /// The branch condition determined by analyzeBranch.
SmallVector<MachineOperand, 4> Cond;
/// Instructions in Head that define values used by the conditional blocks.
@@ -486,18 +486,18 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB, bool Predicate) {
// This is weird, probably some sort of degenerate CFG.
if (!TBB) {
- LLVM_DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n");
+ LLVM_DEBUG(dbgs() << "analyzeBranch didn't find conditional branch.\n");
return false;
}
// Make sure the analyzed branch is conditional; one of the successors
// could be a landing pad. (Empty landing pads can be generated on Windows.)
if (Cond.empty()) {
- LLVM_DEBUG(dbgs() << "AnalyzeBranch found an unconditional branch.\n");
+ LLVM_DEBUG(dbgs() << "analyzeBranch found an unconditional branch.\n");
return false;
}
- // AnalyzeBranch doesn't set FBB on a fall-through branch.
+ // analyzeBranch doesn't set FBB on a fall-through branch.
// Make sure it is always set.
FBB = TBB == Succ0 ? Succ1 : Succ0;
diff --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index f433c4b6c90b..ec19466ea1b3 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1117,7 +1117,7 @@ bool MachineBasicBlock::canSplitCriticalEdge(
return false;
// We may need to update this's terminator, but we can't do that if
- // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
+ // analyzeBranch fails. If this uses a jump table, we won't touch it.
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
SmallVector<MachineOperand, 4> Cond;
@@ -1234,7 +1234,7 @@ bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
MachineBasicBlock *DestB,
bool IsCond) {
// The values of DestA and DestB frequently come from a call to the
- // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
+ // 'TargetInstrInfo::analyzeBranch' method. We take our meaning of the initial
// values from there.
//
// 1. If both DestA and DestB are null, then the block ends with no branches
diff --git a/llvm/lib/CodeGen/MachineBlockPlacement.cpp b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
index 30b98ec88c24..fc52bdb87ccf 100644
--- a/llvm/lib/CodeGen/MachineBlockPlacement.cpp
+++ b/llvm/lib/CodeGen/MachineBlockPlacement.cpp
@@ -2616,7 +2616,7 @@ void MachineBlockPlacement::buildLoopChains(const MachineLoop &L) {
void MachineBlockPlacement::buildCFGChains() {
// Ensure that every BB in the function has an associated chain to simplify
// the assumptions of the remaining algorithm.
- SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
+ SmallVector<MachineOperand, 4> Cond; // For analyzeBranch.
for (MachineFunction::iterator FI = F->begin(), FE = F->end(); FI != FE;
++FI) {
MachineBasicBlock *BB = &*FI;
@@ -2626,7 +2626,7 @@ void MachineBlockPlacement::buildCFGChains() {
// the exact fallthrough behavior for.
while (true) {
Cond.clear();
- MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch.
+ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch.
if (!TII->analyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough())
break;
@@ -2711,7 +2711,7 @@ void MachineBlockPlacement::buildCFGChains() {
// than assert when the branch cannot be analyzed in order to remove this
// boiler plate.
Cond.clear();
- MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch.
+ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch.
#ifndef NDEBUG
if (!BlocksWithUnanalyzableExits.count(PrevBB)) {
@@ -2753,7 +2753,7 @@ void MachineBlockPlacement::buildCFGChains() {
// Fixup the last block.
Cond.clear();
- MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch.
+ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch.
if (!TII->analyzeBranch(F->back(), TBB, FBB, Cond))
F->back().updateTerminator();
@@ -2763,17 +2763,17 @@ void MachineBlockPlacement::buildCFGChains() {
void MachineBlockPlacement::optimizeBranches() {
BlockChain &FunctionChain = *BlockToChain[&F->front()];
- SmallVector<MachineOperand, 4> Cond; // For AnalyzeBranch.
+ SmallVector<MachineOperand, 4> Cond; // For analyzeBranch.
// Now that all the basic blocks in the chain have the proper layout,
- // make a final call to AnalyzeBranch with AllowModify set.
+ // make a final call to analyzeBranch with AllowModify set.
// Indeed, the target may be able to optimize the branches in a way we
// cannot because all branches may not be analyzable.
// E.g., the target may be able to remove an unconditional branch to
// a fallthrough when it occurs after predicated terminators.
for (MachineBasicBlock *ChainBB : FunctionChain) {
Cond.clear();
- MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch.
+ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For analyzeBranch.
if (!TII->analyzeBranch(*ChainBB, TBB, FBB, Cond, /*AllowModify*/ true)) {
// If PrevBB has a two-way branch, try to re-order the branches
// such that we branch to the successor with higher probability first.
diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index 6c0402df8489..5513228f514f 100644
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -669,12 +669,12 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
!isScopedEHPersonality(classifyEHPersonality(F.getPersonalityFn())))
report("MBB has more than one landing pad successor", MBB);
- // Call AnalyzeBranch. If it succeeds, there several more conditions to check.
+ // Call analyzeBranch. If it succeeds, there several more conditions to check.
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
SmallVector<MachineOperand, 4> Cond;
if (!TII->analyzeBranch(*const_cast<MachineBasicBlock *>(MBB), TBB, FBB,
Cond)) {
- // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
+ // Ok, analyzeBranch thinks it knows what's going on with this block. Let's
// check whether its answers match up with reality.
if (!TBB && !FBB) {
// Block falls through to its successor.
@@ -791,7 +791,7 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) {
"condition!", MBB);
}
} else {
- report("AnalyzeBranch returned invalid data!", MBB);
+ report("analyzeBranch returned invalid data!", MBB);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
index 51b2ce029701..894be8b9a9d2 100644
--- a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
@@ -299,7 +299,7 @@ void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,
++NumConditionsAdjusted;
}
-// Parse a condition code returned by AnalyzeBranch, and compute the CondCode
+// Parse a condition code returned by analyzeBranch, and compute the CondCode
// corresponding to TBB.
// Returns true if parsing was successful, otherwise false is returned.
static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
index 054ef8f482ca..70412f877aa0 100644
--- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
@@ -157,7 +157,7 @@ public:
MachineInstr *CmpMI;
private:
- /// The branch condition in Head as determined by AnalyzeBranch.
+ /// The branch condition in Head as determined by analyzeBranch.
SmallVector<MachineOperand, 4> HeadCond;
/// The condition code that makes Head branch to CmpBB.
@@ -267,7 +267,7 @@ bool SSACCmpConv::isDeadDef(unsigned DstReg) {
return MRI->use_nodbg_empty(DstReg);
}
-// Parse a condition code returned by AnalyzeBranch, and compute the CondCode
+// Parse a condition code returned by analyzeBranch, and compute the CondCode
// corresponding to TBB.
// Return
static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
@@ -509,7 +509,7 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
// landing pad.
if (!TBB || HeadCond.empty()) {
LLVM_DEBUG(
- dbgs() << "AnalyzeBranch didn't find conditional branch in Head.\n");
+ dbgs() << "analyzeBranch didn't find conditional branch in Head.\n");
++NumHeadBranchRejs;
return false;
}
@@ -536,7 +536,7 @@ bool SSACCmpConv::canConvert(MachineBasicBlock *MBB) {
if (!TBB || CmpBBCond.empty()) {
LLVM_DEBUG(
- dbgs() << "AnalyzeBranch didn't find conditional branch in CmpBB.\n");
+ dbgs() << "analyzeBranch didn't find conditional branch in CmpBB.\n");
++NumCmpBranchRejs;
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
index 346296c77377..5e97a09dbcc5 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
@@ -676,7 +676,7 @@ bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB,
MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const {
- // Most of the following comes from the ARM implementation of AnalyzeBranch
+ // Most of the following comes from the ARM implementation of analyzeBranch
// If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.cpp b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
index 2bf2c1f6bbc5..c0385ae9550c 100644
--- a/llvm/lib/Target/ARC/ARCInstrInfo.cpp
+++ b/llvm/lib/Target/ARC/ARCInstrInfo.cpp
@@ -161,7 +161,7 @@ static bool isJumpOpcode(int Opc) { return Opc == ARC::J; }
/// condition. These operands can be passed to other TargetInstrInfo
/// methods to create new branches.
///
-/// Note that RemoveBranch and InsertBranch must be implemented to support
+/// Note that RemoveBranch and insertBranch must be implemented to support
/// cases where this method returns success.
///
/// If AllowModify is true, then this routine is allowed to modify the basic
@@ -375,7 +375,7 @@ unsigned ARCInstrInfo::insertBranch(MachineBasicBlock &MBB,
assert(!BytesAdded && "Code size not handled.");
// Shouldn't be a fall through.
- assert(TBB && "InsertBranch must not be told to insert a fallthrough");
+ assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 0) &&
"ARC branch conditions have two components!");
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 1cf1500bc832..2da2511648e8 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -640,7 +640,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
if (!TB || (FB && TB != Header && FB != Header))
return nullptr;
- // Branches of form "if (!P) ..." cause HexagonInstrInfo::AnalyzeBranch
+ // Branches of form "if (!P) ..." cause HexagonInstrInfo::analyzeBranch
// to put imm(0), followed by P in the vector Cond.
// If TB is not the header, it means that the "not-taken" path must lead
// to the header.
@@ -1657,7 +1657,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
MachineBasicBlock *TB = nullptr, *FB = nullptr;
SmallVector<MachineOperand,2> Cond;
- // AnalyzeBranch returns true if it fails to analyze branch.
+ // analyzeBranch returns true if it fails to analyze branch.
bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false);
if (NotAnalyzed || Cond.empty())
return false;
@@ -1693,7 +1693,7 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) {
// Expecting a predicate register as a condition. It won't be a hardware
// predicate register at this point yet, just a vreg.
- // HexagonInstrInfo::AnalyzeBranch for negated branches inserts imm(0)
+ // HexagonInstrInfo::analyzeBranch for negated branches inserts imm(0)
// into Cond, followed by the predicate register. For non-negated branches
// it's just the register.
unsigned CSz = Cond.size();
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 39ec8936214e..9c424bad1393 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -370,7 +370,7 @@ bool HexagonInstrInfo::hasStoreToStackSlot(
/// This function can analyze one/two way branching only and should (mostly) be
/// called by target independent side.
/// First entry is always the opcode of the branching instruction, except when
-/// the Cond vector is supposed to be empty, e.g., when AnalyzeBranch fails, a
+/// the Cond vector is supposed to be empty, e.g., when analyzeBranch fails, a
/// BB with only unconditional jump. Subsequent entries depend upon the opcode,
/// e.g. Jump_c p will have
/// Cond[0] = Jump_c
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
index 676f6f0a2a8c..f54cf6a6a1b1 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.h
@@ -109,19 +109,19 @@ public:
bool AllowModify) const override;
/// Remove the branching code at the end of the specific MBB.
- /// This is only invoked in cases where AnalyzeBranch returns success. It
+ /// This is only invoked in cases where analyzeBranch returns success. It
/// returns the number of instructions that were removed.
unsigned removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved = nullptr) const override;
/// Insert branch code into the end of the specified MachineBasicBlock.
/// The operands to this method are the same as those
- /// returned by AnalyzeBranch. This is only invoked in cases where
- /// AnalyzeBranch returns success. It returns the number of instructions
+ /// returned by analyzeBranch. This is only invoked in cases where
+ /// analyzeBranch returns success. It returns the number of instructions
/// inserted.
///
/// It is also invoked by tail merging to add unconditional branches in
- /// cases where AnalyzeBranch doesn't apply because there was no original
+ /// cases where analyzeBranch doesn't apply because there was no original
/// branch to analyze. At least this much must be implemented, else tail
/// merging needs to be disabled.
unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
diff --git a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
index c13ee08e1213..749bc623338d 100644
--- a/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
+++ b/llvm/lib/Target/Lanai/LanaiAsmPrinter.cpp
@@ -211,7 +211,7 @@ void LanaiAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// isBlockOnlyReachableByFallthough - Return true if the basic block has
// exactly one predecessor and the control transfer mechanism between
// the predecessor and this block is a fall-through.
-// FIXME: could the overridden cases be handled in AnalyzeBranch?
+// FIXME: could the overridden cases be handled in analyzeBranch?
bool LanaiAsmPrinter::isBlockOnlyReachableByFallthrough(
const MachineBasicBlock *MBB) const {
// The predecessor has to be immediately before this block.
diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
index cff230289e60..ec0c92ccf5c5 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.cpp
@@ -69,7 +69,7 @@ void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, getKillRegState(KillSrc));
}
-/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
+/// analyzeBranch - Analyze the branching code at the end of MBB, returning
/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
/// implemented for a target). Upon success, this returns false and returns
/// with the following information in various cases:
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index f6bc52968a33..6ddd5f40a4e8 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -342,7 +342,7 @@ unsigned RISCVInstrInfo::insertBranch(
*BytesAdded = 0;
// Shouldn't be a fall through.
- assert(TBB && "InsertBranch must not be told to insert a fallthrough");
+ assert(TBB && "insertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 3 || Cond.size() == 0) &&
"RISCV branch conditions have two components!");
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
index c069af9eed62..b4354e852194 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyCFGSort.cpp
@@ -152,7 +152,7 @@ static void maybeUpdateTerminator(MachineBasicBlock *MBB) {
AllAnalyzable &= Term.isBranch() && !Term.isIndirectBranch();
}
assert((AnyBarrier || AllAnalyzable) &&
- "AnalyzeBranch needs to analyze any block with a fallthrough");
+ "analyzeBranch needs to analyze any block with a fallthrough");
if (AllAnalyzable)
MBB->updateTerminator();
}
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
index a4f8dd669e1e..eb94237180df 100644
--- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
+++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -91,7 +91,7 @@ namespace X86 {
COND_G = 15,
LAST_VALID_COND = COND_G,
- // Artificial condition codes. These are used by AnalyzeBranch
+ // Artificial condition codes. These are used by analyzeBranch
// to indicate a block terminated with two conditional branches that together
// form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
// which can't be represented on x86 with a single condition. These
diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
index db44a56be538..593decdb3af8 100644
--- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -163,7 +163,7 @@ static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
}
}
-/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
+/// analyzeBranch - Analyze the branching code at the end of MBB, returning
/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
/// implemented for a target). Upon success, this returns false and returns
/// with the following information in various cases:
diff --git a/llvm/test/CodeGen/SystemZ/branch-08.ll b/llvm/test/CodeGen/SystemZ/branch-08.ll
index 41ca8ac99713..237676937cab 100644
--- a/llvm/test/CodeGen/SystemZ/branch-08.ll
+++ b/llvm/test/CodeGen/SystemZ/branch-08.ll
@@ -1,4 +1,4 @@
-; Test SystemZInstrInfo::AnalyzeBranch and SystemZInstrInfo::InsertBranch.
+; Test SystemZInstrInfo::analyzeBranch and SystemZInstrInfo::insertBranch.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
diff --git a/llvm/test/CodeGen/SystemZ/int-cmp-02.ll b/llvm/test/CodeGen/SystemZ/int-cmp-02.ll
index b07f6b5d43ff..943f6d8002c5 100644
--- a/llvm/test/CodeGen/SystemZ/int-cmp-02.ll
+++ b/llvm/test/CodeGen/SystemZ/int-cmp-02.ll
@@ -162,7 +162,7 @@ define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
ret double %res
}
-; The first branch here got recreated by InsertBranch while splitting the
+; The first branch here got recreated by insertBranch while splitting the
; critical edge %entry->%while.body, which lost the kills information for CC.
define void @f12(i32 %a, i32 %b) {
; CHECK-LABEL: f12: