forked from OSchip/llvm-project
[RISCV][Clang] Add RVV Type-Convert intrinsic functions.
Fix extension macro condition. Support below instructions: 1. Single-Width Floating-Point/Integer Type-Convert Instructions 2. Widening Floating-Point/Integer Type-Convert Instructions 3. Narrowing Floating-Point/Integer Type-Convert Instructions Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D99742
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@ -379,6 +379,31 @@ class RVVFloatingUnaryBuiltin<string builtin_suffix, string ir_suffix,
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class RVVFloatingUnaryVVBuiltin : RVVFloatingUnaryBuiltin<"v", "v", "vv">;
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class RVVConvBuiltin<string suffix, string prototype, string type_range,
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string mangled_name>
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: RVVBuiltin<suffix, prototype, type_range> {
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let IntrinsicTypes = [-1, 0];
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let MangledName = mangled_name;
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}
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class RVVConvToSignedBuiltin<string mangled_name>
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: RVVConvBuiltin<"Iv", "Ivv", "fd", mangled_name>;
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class RVVConvToUnsignedBuiltin<string mangled_name>
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: RVVConvBuiltin<"Uv", "Uvv", "fd", mangled_name>;
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class RVVConvToWidenSignedBuiltin<string mangled_name>
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: RVVConvBuiltin<"Iw", "Iwv", "f", mangled_name>;
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class RVVConvToWidenUnsignedBuiltin<string mangled_name>
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: RVVConvBuiltin<"Uw", "Uwv", "f", mangled_name>;
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class RVVConvToNarrowingSignedBuiltin<string mangled_name>
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: RVVConvBuiltin<"Iv", "IvFw", "si", mangled_name>;
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class RVVConvToNarrowingUnsignedBuiltin<string mangled_name>
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: RVVConvBuiltin<"Uv", "UvFw", "si", mangled_name>;
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// For widen operation which has different mangling name.
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multiclass RVVWidenBuiltinSet<string intrinsic_name, string type_range,
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list<list<string>> suffixes_prototypes> {
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@ -899,10 +924,32 @@ let Name = "vfmerge_vfm", HasMask = false, PermuteOperands = [2, 0, 1] in
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// TODO
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// 14.17. Single-Width Floating-Point/Integer Type-Convert Instructions
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// TODO
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def vfcvt_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_xu">;
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def vfcvt_x_f_v : RVVConvToSignedBuiltin<"vfcvt_x">;
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def vfcvt_rtz_xu_f_v : RVVConvToUnsignedBuiltin<"vfcvt_rtz_xu">;
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def vfcvt_rtz_x_f_v : RVVConvToSignedBuiltin<"vfcvt_rtz_x">;
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def vfcvt_f_xu_v : RVVConvBuiltin<"Fv", "FvUv", "sil", "vfcvt_f">;
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def vfcvt_f_x_v : RVVConvBuiltin<"Fv", "Fvv", "sil", "vfcvt_f">;
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// 14.18. Widening Floating-Point/Integer Type-Convert Instructions
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// TODO
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let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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def vfwcvt_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_xu">;
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def vfwcvt_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_x">;
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def vfwcvt_rtz_xu_f_v : RVVConvToWidenUnsignedBuiltin<"vfwcvt_rtz_xu">;
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def vfwcvt_rtz_x_f_v : RVVConvToWidenSignedBuiltin<"vfwcvt_rtz_x">;
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def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
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def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
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def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "hf", "vfwcvt_f">;
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}
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// 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
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// TODO
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let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
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def vfncvt_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_xu">;
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def vfncvt_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_x">;
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def vfncvt_rtz_xu_f_w : RVVConvToNarrowingUnsignedBuiltin<"vfncvt_rtz_xu">;
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def vfncvt_rtz_x_f_w : RVVConvToNarrowingSignedBuiltin<"vfncvt_rtz_x">;
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def vfncvt_f_xu_w : RVVConvBuiltin<"Fv", "FvUw", "si", "vfncvt_f">;
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def vfncvt_f_x_w : RVVConvBuiltin<"Fv", "Fvw", "si", "vfncvt_f">;
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def vfncvt_f_f_w : RVVConvBuiltin<"v", "vw", "f", "vfncvt_f">;
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def vfncvt_rod_f_f_w : RVVConvBuiltin<"v", "vw", "f", "vfncvt_rod_f">;
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}
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@ -1177,7 +1177,7 @@ bool RVVEmitter::emitExtDefStr(uint8_t Extents, raw_ostream &OS) {
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if (Extents == RISCVExtension::Basic)
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return false;
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OS << "#if ";
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ListSeparator LS(" || ");
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ListSeparator LS(" && ");
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if (Extents & RISCVExtension::F)
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OS << LS << "defined(__riscv_f)";
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if (Extents & RISCVExtension::D)
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