forked from OSchip/llvm-project
Move BaseIndexOffset in DAGCombiner.cpp so it will be available for the upcoming user
llvm-svn: 289537
This commit is contained in:
Artur Pilipenko
parent
de82a65053
commit
01e86444a0
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@ -4236,6 +4236,110 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
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return nullptr;
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}
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namespace {
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/// Helper struct to parse and store a memory address as base + index + offset.
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/// We ignore sign extensions when it is safe to do so.
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/// The following two expressions are not equivalent. To differentiate we need
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/// to store whether there was a sign extension involved in the index
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/// computation.
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/// (load (i64 add (i64 copyfromreg %c)
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/// (i64 signextend (add (i8 load %index)
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/// (i8 1))))
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/// vs
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///
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/// (load (i64 add (i64 copyfromreg %c)
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/// (i64 signextend (i32 add (i32 signextend (i8 load %index))
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/// (i32 1)))))
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struct BaseIndexOffset {
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SDValue Base;
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SDValue Index;
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int64_t Offset;
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bool IsIndexSignExt;
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BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
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BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
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bool IsIndexSignExt) :
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Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
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bool equalBaseIndex(const BaseIndexOffset &Other) {
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return Other.Base == Base && Other.Index == Index &&
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Other.IsIndexSignExt == IsIndexSignExt;
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}
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/// Parses tree in Ptr for base, index, offset addresses.
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static BaseIndexOffset match(SDValue Ptr, SelectionDAG &DAG) {
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bool IsIndexSignExt = false;
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// Split up a folded GlobalAddress+Offset into its component parts.
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if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Ptr))
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if (GA->getOpcode() == ISD::GlobalAddress && GA->getOffset() != 0) {
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return BaseIndexOffset(DAG.getGlobalAddress(GA->getGlobal(),
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SDLoc(GA),
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GA->getValueType(0),
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/*Offset=*/0,
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/*isTargetGA=*/false,
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GA->getTargetFlags()),
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SDValue(),
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GA->getOffset(),
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IsIndexSignExt);
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}
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// We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
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// instruction, then it could be just the BASE or everything else we don't
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// know how to handle. Just use Ptr as BASE and give up.
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if (Ptr->getOpcode() != ISD::ADD)
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return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
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// We know that we have at least an ADD instruction. Try to pattern match
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// the simple case of BASE + OFFSET.
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if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
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int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
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return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
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IsIndexSignExt);
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}
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// Inside a loop the current BASE pointer is calculated using an ADD and a
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// MUL instruction. In this case Ptr is the actual BASE pointer.
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// (i64 add (i64 %array_ptr)
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// (i64 mul (i64 %induction_var)
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// (i64 %element_size)))
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if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
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return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
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// Look at Base + Index + Offset cases.
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SDValue Base = Ptr->getOperand(0);
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SDValue IndexOffset = Ptr->getOperand(1);
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// Skip signextends.
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if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
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IndexOffset = IndexOffset->getOperand(0);
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IsIndexSignExt = true;
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}
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// Either the case of Base + Index (no offset) or something else.
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if (IndexOffset->getOpcode() != ISD::ADD)
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return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
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// Now we have the case of Base + Index + offset.
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SDValue Index = IndexOffset->getOperand(0);
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SDValue Offset = IndexOffset->getOperand(1);
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if (!isa<ConstantSDNode>(Offset))
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return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
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// Ignore signextends.
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if (Index->getOpcode() == ISD::SIGN_EXTEND) {
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Index = Index->getOperand(0);
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IsIndexSignExt = true;
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} else IsIndexSignExt = false;
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int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
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return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
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}
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};
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} // namespace
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SDValue DAGCombiner::visitXOR(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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@ -11217,110 +11321,6 @@ SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
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return SDValue();
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}
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namespace {
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/// Helper struct to parse and store a memory address as base + index + offset.
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/// We ignore sign extensions when it is safe to do so.
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/// The following two expressions are not equivalent. To differentiate we need
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/// to store whether there was a sign extension involved in the index
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/// computation.
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/// (load (i64 add (i64 copyfromreg %c)
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/// (i64 signextend (add (i8 load %index)
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/// (i8 1))))
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/// vs
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///
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/// (load (i64 add (i64 copyfromreg %c)
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/// (i64 signextend (i32 add (i32 signextend (i8 load %index))
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/// (i32 1)))))
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struct BaseIndexOffset {
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SDValue Base;
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SDValue Index;
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int64_t Offset;
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bool IsIndexSignExt;
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BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {}
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BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset,
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bool IsIndexSignExt) :
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Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {}
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bool equalBaseIndex(const BaseIndexOffset &Other) {
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return Other.Base == Base && Other.Index == Index &&
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Other.IsIndexSignExt == IsIndexSignExt;
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}
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/// Parses tree in Ptr for base, index, offset addresses.
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static BaseIndexOffset match(SDValue Ptr, SelectionDAG &DAG) {
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bool IsIndexSignExt = false;
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// Split up a folded GlobalAddress+Offset into its component parts.
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if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Ptr))
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if (GA->getOpcode() == ISD::GlobalAddress && GA->getOffset() != 0) {
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return BaseIndexOffset(DAG.getGlobalAddress(GA->getGlobal(),
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SDLoc(GA),
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GA->getValueType(0),
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/*Offset=*/0,
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/*isTargetGA=*/false,
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GA->getTargetFlags()),
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SDValue(),
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GA->getOffset(),
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IsIndexSignExt);
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}
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// We only can pattern match BASE + INDEX + OFFSET. If Ptr is not an ADD
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// instruction, then it could be just the BASE or everything else we don't
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// know how to handle. Just use Ptr as BASE and give up.
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if (Ptr->getOpcode() != ISD::ADD)
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return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
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// We know that we have at least an ADD instruction. Try to pattern match
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// the simple case of BASE + OFFSET.
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if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
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int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
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return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
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IsIndexSignExt);
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}
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// Inside a loop the current BASE pointer is calculated using an ADD and a
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// MUL instruction. In this case Ptr is the actual BASE pointer.
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// (i64 add (i64 %array_ptr)
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// (i64 mul (i64 %induction_var)
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// (i64 %element_size)))
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if (Ptr->getOperand(1)->getOpcode() == ISD::MUL)
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return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
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// Look at Base + Index + Offset cases.
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SDValue Base = Ptr->getOperand(0);
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SDValue IndexOffset = Ptr->getOperand(1);
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// Skip signextends.
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if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) {
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IndexOffset = IndexOffset->getOperand(0);
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IsIndexSignExt = true;
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}
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// Either the case of Base + Index (no offset) or something else.
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if (IndexOffset->getOpcode() != ISD::ADD)
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return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt);
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// Now we have the case of Base + Index + offset.
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SDValue Index = IndexOffset->getOperand(0);
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SDValue Offset = IndexOffset->getOperand(1);
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if (!isa<ConstantSDNode>(Offset))
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return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
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// Ignore signextends.
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if (Index->getOpcode() == ISD::SIGN_EXTEND) {
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Index = Index->getOperand(0);
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IsIndexSignExt = true;
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} else IsIndexSignExt = false;
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int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
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return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
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}
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};
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} // namespace
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// This is a helper function for visitMUL to check the profitability
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// of folding (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2).
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// MulNode is the original multiply, AddNode is (add x, c1),
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