forked from OSchip/llvm-project
parent
a15b0ebb5e
commit
01dd97a8aa
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@ -210,13 +210,15 @@ let Defs = [R0] in {
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def UMULL : IntBinOp<"umull r12,", mulhu>;
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}
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def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
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"b$cc $dst",
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[(armbr bb:$dst, imm:$cc)]>;
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let isTerminator = 1 in {
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def bcond : InstARM<(ops brtarget:$dst, CCOp:$cc),
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"b$cc $dst",
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[(armbr bb:$dst, imm:$cc)]>;
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def b : InstARM<(ops brtarget:$dst),
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"b $dst",
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[(br bb:$dst)]>;
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def b : InstARM<(ops brtarget:$dst),
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"b $dst",
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[(br bb:$dst)]>;
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}
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def cmp : InstARM<(ops IntRegs:$a, op_addr_mode1:$b),
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"cmp $a, $b",
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