forked from OSchip/llvm-project
[NFC][Alignment] Use getAlign in ARMFastISel
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@ -188,10 +188,10 @@ class ARMFastISel final : public FastISel {
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bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
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bool isZExt);
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bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
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unsigned Alignment = 0, bool isZExt = true,
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MaybeAlign Alignment = None, bool isZExt = true,
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bool allocReg = true);
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bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment = 0);
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MaybeAlign Alignment = None);
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bool ARMComputeAddress(const Value *Obj, Address &Addr);
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void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3);
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bool ARMIsMemCpySmall(uint64_t Len);
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@ -897,7 +897,8 @@ void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr,
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}
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bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
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unsigned Alignment, bool isZExt, bool allocReg) {
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MaybeAlign Alignment, bool isZExt,
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bool allocReg) {
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unsigned Opc;
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bool useAM3 = false;
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bool needVMOV = false;
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@ -923,7 +924,8 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
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RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
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break;
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case MVT::i16:
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if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
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if (Alignment && *Alignment < Align(2) &&
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!Subtarget->allowsUnalignedMem())
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return false;
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if (isThumb2) {
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@ -938,7 +940,8 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
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RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
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break;
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case MVT::i32:
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if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
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if (Alignment && *Alignment < Align(4) &&
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!Subtarget->allowsUnalignedMem())
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return false;
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if (isThumb2) {
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@ -954,7 +957,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
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case MVT::f32:
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if (!Subtarget->hasVFP2Base()) return false;
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// Unaligned loads need special handling. Floats require word-alignment.
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if (Alignment && Alignment < 4) {
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if (Alignment && *Alignment < Align(4)) {
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needVMOV = true;
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VT = MVT::i32;
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Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
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@ -969,7 +972,7 @@ bool ARMFastISel::ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
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if (!Subtarget->hasVFP2Base()) return false;
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// FIXME: Unaligned loads need special handling. Doublewords require
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// word-alignment.
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if (Alignment && Alignment < 4)
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if (Alignment && *Alignment < Align(4))
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return false;
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Opc = ARM::VLDRD;
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@ -1029,14 +1032,14 @@ bool ARMFastISel::SelectLoad(const Instruction *I) {
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if (!ARMComputeAddress(I->getOperand(0), Addr)) return false;
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Register ResultReg;
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if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment()))
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if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlign()))
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return false;
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updateValueMap(I, ResultReg);
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return true;
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}
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bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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unsigned Alignment) {
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MaybeAlign Alignment) {
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unsigned StrOpc;
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bool useAM3 = false;
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switch (VT.SimpleTy) {
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@ -1064,7 +1067,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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}
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break;
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case MVT::i16:
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if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem())
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if (Alignment && *Alignment < Align(2) &&
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!Subtarget->allowsUnalignedMem())
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return false;
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if (isThumb2) {
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@ -1078,7 +1082,8 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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}
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break;
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case MVT::i32:
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if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem())
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if (Alignment && *Alignment < Align(4) &&
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!Subtarget->allowsUnalignedMem())
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return false;
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if (isThumb2) {
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@ -1093,7 +1098,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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case MVT::f32:
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if (!Subtarget->hasVFP2Base()) return false;
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// Unaligned stores need special handling. Floats require word-alignment.
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if (Alignment && Alignment < 4) {
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if (Alignment && *Alignment < Align(4)) {
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Register MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(ARM::VMOVRS), MoveReg)
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@ -1110,7 +1115,7 @@ bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr,
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if (!Subtarget->hasVFP2Base()) return false;
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// FIXME: Unaligned stores need special handling. Doublewords require
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// word-alignment.
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if (Alignment && Alignment < 4)
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if (Alignment && *Alignment < Align(4))
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return false;
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StrOpc = ARM::VSTRD;
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@ -1165,7 +1170,7 @@ bool ARMFastISel::SelectStore(const Instruction *I) {
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if (!ARMComputeAddress(I->getOperand(1), Addr))
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return false;
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if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment()))
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if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlign()))
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return false;
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return true;
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}
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@ -2938,7 +2943,7 @@ bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
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if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false;
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Register ResultReg = MI->getOperand(0).getReg();
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if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false))
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if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlign(), isZExt, false))
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return false;
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MachineBasicBlock::iterator I(MI);
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removeDeadCode(I, std::next(I));
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