forked from OSchip/llvm-project
[codegen,amdgpu] Enhance MIR DIE and re-arrange it for AMDGPU.
Summary: - `dead-mi-elimination` assumes MIR in the SSA form and cannot be arranged after phi elimination or DeSSA. It's enhanced to handle the dead register definition by skipping use check on it. Once a register def is `dead`, all its uses, if any, should be `undef`. - Re-arrange the DIE in RA phase for AMDGPU by placing it directly after `detect-dead-lanes`. - Many relevant tests are refined due to different register assignment. Reviewers: rampitec, qcolombet, sunfish Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72709
This commit is contained in:
Michael Liao
parent
47c6ab2b97
commit
01a4b83154
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@ -82,6 +82,15 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
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if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
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return false;
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} else {
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if (MO.isDead()) {
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#ifndef NDEBUG
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// Sanity check on uses of this dead register. All of them should be
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// 'undef'.
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for (auto &U : MRI->use_nodbg_operands(Reg))
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assert(U.isUndef() && "'Undef' use on a 'dead' register is found!");
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#endif
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continue;
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}
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for (const MachineInstr &Use : MRI->use_nodbg_instructions(Reg)) {
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if (&Use != MI)
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// This def has a non-debug use. Don't delete the instruction!
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@ -948,7 +948,7 @@ void GCNPassConfig::addOptimizedRegAlloc() {
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insertPass(&RegisterCoalescerID, &SIPreAllocateWWMRegsID, false);
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if (EnableDCEInRA)
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insertPass(&RenameIndependentSubregsID, &DeadMachineInstructionElimID);
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insertPass(&DetectDeadLanesID, &DeadMachineInstructionElimID);
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TargetPassConfig::addOptimizedRegAlloc();
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}
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@ -1205,20 +1205,20 @@ define amdgpu_kernel void @add_i64_constant(i64 addrspace(1)* %out) {
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;
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; GFX1064-LABEL: add_i64_constant:
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; GFX1064: ; %bb.0: ; %entry
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; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0
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; GFX1064-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0
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; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2
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; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0
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; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s5, v0
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; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; GFX1064-NEXT: ; mask branch BB5_2
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; GFX1064-NEXT: s_cbranch_execz BB5_2
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; GFX1064-NEXT: BB5_1:
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; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
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; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
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; GFX1064-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo
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; GFX1064-NEXT: v_mul_hi_u32_u24_e64 v2, s2, 5
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; GFX1064-NEXT: v_mul_u32_u24_e64 v1, s2, 5
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; GFX1064-NEXT: v_mul_hi_u32_u24_e64 v2, s4, 5
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; GFX1064-NEXT: v_mul_u32_u24_e64 v1, s4, 5
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; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX1064-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2]
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@ -1227,7 +1227,7 @@ define amdgpu_kernel void @add_i64_constant(i64 addrspace(1)* %out) {
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; GFX1064-NEXT: buffer_gl1_inv
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; GFX1064-NEXT: BB5_2:
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; GFX1064-NEXT: v_nop
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; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
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; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
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; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
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; GFX1064-NEXT: v_readfirstlane_b32 s3, v2
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; GFX1064-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v0, 5, s[2:3]
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@ -2310,20 +2310,20 @@ define amdgpu_kernel void @sub_i64_constant(i64 addrspace(1)* %out) {
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;
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; GFX1064-LABEL: sub_i64_constant:
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; GFX1064: ; %bb.0: ; %entry
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; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0
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; GFX1064-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0
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; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2
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; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0
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; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
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; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s5, v0
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; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
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; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc
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; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; GFX1064-NEXT: ; mask branch BB11_2
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; GFX1064-NEXT: s_cbranch_execz BB11_2
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; GFX1064-NEXT: BB11_1:
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; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
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; GFX1064-NEXT: s_bcnt1_i32_b64 s4, s[4:5]
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; GFX1064-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo
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; GFX1064-NEXT: v_mul_hi_u32_u24_e64 v2, s2, 5
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; GFX1064-NEXT: v_mul_u32_u24_e64 v1, s2, 5
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; GFX1064-NEXT: v_mul_hi_u32_u24_e64 v2, s4, 5
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; GFX1064-NEXT: v_mul_u32_u24_e64 v1, s4, 5
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; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0
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; GFX1064-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2]
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@ -2332,7 +2332,7 @@ define amdgpu_kernel void @sub_i64_constant(i64 addrspace(1)* %out) {
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; GFX1064-NEXT: buffer_gl1_inv
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; GFX1064-NEXT: BB11_2:
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; GFX1064-NEXT: v_nop
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; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
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; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3]
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; GFX1064-NEXT: v_readfirstlane_b32 s2, v1
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; GFX1064-NEXT: v_mul_u32_u24_e32 v1, 5, v0
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; GFX1064-NEXT: v_readfirstlane_b32 s3, v2
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@ -189,41 +189,41 @@ define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i
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;
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; VI-LABEL: test_bswap_v8i32:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s12, 0xff00ff
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; VI-NEXT: s_mov_b32 s11, 0xf000
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; VI-NEXT: s_mov_b32 s10, -1
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s8, s0
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; VI-NEXT: s_mov_b32 s9, s1
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; VI-NEXT: s_load_dwordx8 s[0:7], s[2:3], 0x0
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_load_dwordx8 s[4:11], s[6:7], 0x0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_alignbit_b32 v0, s3, s3, 8
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; VI-NEXT: v_alignbit_b32 v1, s3, s3, 24
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; VI-NEXT: v_alignbit_b32 v0, s7, s7, 8
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; VI-NEXT: v_alignbit_b32 v1, s7, s7, 24
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; VI-NEXT: v_bfi_b32 v3, s12, v1, v0
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; VI-NEXT: v_alignbit_b32 v2, s2, s2, 8
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; VI-NEXT: v_alignbit_b32 v4, s2, s2, 24
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; VI-NEXT: v_alignbit_b32 v0, s1, s1, 8
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; VI-NEXT: v_alignbit_b32 v1, s1, s1, 24
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; VI-NEXT: v_alignbit_b32 v2, s6, s6, 8
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; VI-NEXT: v_alignbit_b32 v4, s6, s6, 24
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; VI-NEXT: v_alignbit_b32 v0, s5, s5, 8
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; VI-NEXT: v_alignbit_b32 v1, s5, s5, 24
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; VI-NEXT: v_bfi_b32 v2, s12, v4, v2
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; VI-NEXT: v_bfi_b32 v1, s12, v1, v0
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; VI-NEXT: v_alignbit_b32 v0, s0, s0, 8
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; VI-NEXT: v_alignbit_b32 v4, s0, s0, 24
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; VI-NEXT: v_alignbit_b32 v0, s4, s4, 8
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; VI-NEXT: v_alignbit_b32 v4, s4, s4, 24
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; VI-NEXT: v_bfi_b32 v0, s12, v4, v0
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; VI-NEXT: v_alignbit_b32 v4, s7, s7, 8
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; VI-NEXT: v_alignbit_b32 v5, s7, s7, 24
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; VI-NEXT: v_alignbit_b32 v4, s11, s11, 8
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; VI-NEXT: v_alignbit_b32 v5, s11, s11, 24
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; VI-NEXT: v_bfi_b32 v7, s12, v5, v4
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; VI-NEXT: v_alignbit_b32 v4, s6, s6, 8
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; VI-NEXT: v_alignbit_b32 v5, s6, s6, 24
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; VI-NEXT: v_alignbit_b32 v4, s10, s10, 8
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; VI-NEXT: v_alignbit_b32 v5, s10, s10, 24
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; VI-NEXT: v_bfi_b32 v6, s12, v5, v4
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; VI-NEXT: v_alignbit_b32 v4, s5, s5, 8
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; VI-NEXT: v_alignbit_b32 v5, s5, s5, 24
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; VI-NEXT: v_alignbit_b32 v4, s9, s9, 8
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; VI-NEXT: v_alignbit_b32 v5, s9, s9, 24
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; VI-NEXT: v_bfi_b32 v5, s12, v5, v4
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; VI-NEXT: v_alignbit_b32 v4, s4, s4, 8
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; VI-NEXT: v_alignbit_b32 v8, s4, s4, 24
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; VI-NEXT: v_alignbit_b32 v4, s8, s8, 8
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; VI-NEXT: v_alignbit_b32 v8, s8, s8, 24
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; VI-NEXT: v_bfi_b32 v4, s12, v8, v4
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; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
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; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
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; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
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; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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%val = load <8 x i32>, <8 x i32> addrspace(1)* %in, align 32
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%bswap = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %val) nounwind readnone
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@ -234,11 +234,11 @@ define amdgpu_kernel void @test_bswap_v8i32(<8 x i32> addrspace(1)* %out, <8 x i
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define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %in) nounwind {
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; SI-LABEL: test_bswap_i64:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_load_dwordx2 s[6:7], s[6:7], 0x0
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_mov_b32 s19, 0xff0000
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; SI-NEXT: s_mov_b32 s9, 0
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; SI-NEXT: s_mov_b32 s15, 0xff00
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@ -247,34 +247,34 @@ define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(
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; SI-NEXT: s_mov_b32 s14, s9
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; SI-NEXT: s_mov_b32 s16, s9
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; SI-NEXT: s_mov_b32 s18, s9
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: s_mov_b32 s0, s4
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; SI-NEXT: s_mov_b32 s1, s5
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: v_mov_b32_e32 v0, s2
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; SI-NEXT: v_alignbit_b32 v1, s3, v0, 24
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; SI-NEXT: v_alignbit_b32 v0, s3, v0, 8
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; SI-NEXT: s_lshr_b32 s8, s3, 24
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; SI-NEXT: s_lshr_b32 s10, s3, 8
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; SI-NEXT: s_lshl_b64 s[0:1], s[2:3], 8
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; SI-NEXT: s_lshl_b64 s[20:21], s[2:3], 24
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; SI-NEXT: s_lshl_b32 s17, s2, 24
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; SI-NEXT: s_lshl_b32 s0, s2, 8
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; SI-NEXT: v_mov_b32_e32 v0, s6
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; SI-NEXT: v_alignbit_b32 v1, s7, v0, 24
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; SI-NEXT: v_alignbit_b32 v0, s7, v0, 8
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; SI-NEXT: s_lshr_b32 s8, s7, 24
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; SI-NEXT: s_lshr_b32 s10, s7, 8
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; SI-NEXT: s_lshl_b64 s[4:5], s[6:7], 8
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; SI-NEXT: s_lshl_b64 s[20:21], s[6:7], 24
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; SI-NEXT: s_lshl_b32 s17, s6, 24
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; SI-NEXT: s_lshl_b32 s4, s6, 8
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; SI-NEXT: v_and_b32_e32 v1, s19, v1
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; SI-NEXT: v_and_b32_e32 v0, 0xff000000, v0
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; SI-NEXT: s_and_b32 s10, s10, s15
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; SI-NEXT: s_and_b32 s13, s1, 0xff
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; SI-NEXT: s_and_b32 s13, s5, 0xff
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; SI-NEXT: s_and_b32 s15, s21, s15
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; SI-NEXT: s_and_b32 s19, s0, s19
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; SI-NEXT: s_and_b32 s19, s4, s19
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; SI-NEXT: v_or_b32_e32 v0, v0, v1
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; SI-NEXT: s_or_b64 s[0:1], s[10:11], s[8:9]
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; SI-NEXT: s_or_b64 s[2:3], s[14:15], s[12:13]
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; SI-NEXT: s_or_b64 s[4:5], s[10:11], s[8:9]
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; SI-NEXT: s_or_b64 s[6:7], s[14:15], s[12:13]
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; SI-NEXT: s_or_b64 s[8:9], s[16:17], s[18:19]
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; SI-NEXT: v_or_b32_e32 v0, s0, v0
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; SI-NEXT: v_mov_b32_e32 v1, s1
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; SI-NEXT: s_or_b64 s[0:1], s[8:9], s[2:3]
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; SI-NEXT: v_or_b32_e32 v0, s0, v0
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; SI-NEXT: v_or_b32_e32 v1, s1, v1
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: v_or_b32_e32 v0, s4, v0
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; SI-NEXT: v_mov_b32_e32 v1, s5
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; SI-NEXT: s_or_b64 s[4:5], s[8:9], s[6:7]
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; SI-NEXT: v_or_b32_e32 v0, s4, v0
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; SI-NEXT: v_or_b32_e32 v1, s5, v1
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: test_bswap_i64:
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@ -328,47 +328,47 @@ define amdgpu_kernel void @test_bswap_i64(i64 addrspace(1)* %out, i64 addrspace(
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define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %in) nounwind {
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; SI-LABEL: test_bswap_v2i64:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
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; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: s_mov_b32 s31, 0xff0000
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_load_dwordx4 s[4:7], s[10:11], 0x0
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; SI-NEXT: s_mov_b32 s11, 0
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; SI-NEXT: s_load_dwordx4 s[8:11], s[6:7], 0x0
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; SI-NEXT: s_mov_b32 s7, 0
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; SI-NEXT: s_mov_b32 s22, 0xff000000
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; SI-NEXT: s_mov_b32 s27, 0xff00
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; SI-NEXT: s_movk_i32 s25, 0xff
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; SI-NEXT: s_mov_b32 s13, s11
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; SI-NEXT: s_mov_b32 s14, s11
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; SI-NEXT: s_mov_b32 s16, s11
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||||
; SI-NEXT: s_mov_b32 s18, s11
|
||||
; SI-NEXT: s_mov_b32 s20, s11
|
||||
; SI-NEXT: s_mov_b32 s23, s11
|
||||
; SI-NEXT: s_mov_b32 s24, s11
|
||||
; SI-NEXT: s_mov_b32 s26, s11
|
||||
; SI-NEXT: s_mov_b32 s28, s11
|
||||
; SI-NEXT: s_mov_b32 s30, s11
|
||||
; SI-NEXT: s_mov_b32 s0, s8
|
||||
; SI-NEXT: s_mov_b32 s1, s9
|
||||
; SI-NEXT: s_mov_b32 s13, s7
|
||||
; SI-NEXT: s_mov_b32 s14, s7
|
||||
; SI-NEXT: s_mov_b32 s16, s7
|
||||
; SI-NEXT: s_mov_b32 s18, s7
|
||||
; SI-NEXT: s_mov_b32 s20, s7
|
||||
; SI-NEXT: s_mov_b32 s23, s7
|
||||
; SI-NEXT: s_mov_b32 s24, s7
|
||||
; SI-NEXT: s_mov_b32 s26, s7
|
||||
; SI-NEXT: s_mov_b32 s28, s7
|
||||
; SI-NEXT: s_mov_b32 s30, s7
|
||||
; SI-NEXT: s_mov_b32 s0, s4
|
||||
; SI-NEXT: s_mov_b32 s1, s5
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s6
|
||||
; SI-NEXT: v_alignbit_b32 v1, s7, v0, 24
|
||||
; SI-NEXT: v_alignbit_b32 v0, s7, v0, 8
|
||||
; SI-NEXT: s_lshr_b32 s10, s7, 24
|
||||
; SI-NEXT: s_lshr_b32 s12, s7, 8
|
||||
; SI-NEXT: s_lshl_b64 s[8:9], s[6:7], 8
|
||||
; SI-NEXT: s_lshl_b64 s[32:33], s[6:7], 24
|
||||
; SI-NEXT: s_lshl_b32 s19, s6, 24
|
||||
; SI-NEXT: s_lshl_b32 s21, s6, 8
|
||||
; SI-NEXT: v_mov_b32_e32 v2, s4
|
||||
; SI-NEXT: v_alignbit_b32 v3, s5, v2, 24
|
||||
; SI-NEXT: v_alignbit_b32 v2, s5, v2, 8
|
||||
; SI-NEXT: s_lshr_b32 s32, s5, 8
|
||||
; SI-NEXT: s_lshl_b64 s[6:7], s[4:5], 8
|
||||
; SI-NEXT: s_and_b32 s15, s9, s25
|
||||
; SI-NEXT: s_lshl_b64 s[8:9], s[4:5], 24
|
||||
; SI-NEXT: s_lshl_b32 s29, s4, 24
|
||||
; SI-NEXT: s_lshl_b32 s4, s4, 8
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s10
|
||||
; SI-NEXT: v_alignbit_b32 v1, s11, v0, 24
|
||||
; SI-NEXT: v_alignbit_b32 v0, s11, v0, 8
|
||||
; SI-NEXT: s_lshr_b32 s6, s11, 24
|
||||
; SI-NEXT: s_lshr_b32 s12, s11, 8
|
||||
; SI-NEXT: s_lshl_b64 s[4:5], s[10:11], 8
|
||||
; SI-NEXT: s_lshl_b64 s[32:33], s[10:11], 24
|
||||
; SI-NEXT: s_lshl_b32 s19, s10, 24
|
||||
; SI-NEXT: s_lshl_b32 s21, s10, 8
|
||||
; SI-NEXT: v_mov_b32_e32 v2, s8
|
||||
; SI-NEXT: v_alignbit_b32 v3, s9, v2, 24
|
||||
; SI-NEXT: v_alignbit_b32 v2, s9, v2, 8
|
||||
; SI-NEXT: s_lshr_b32 s32, s9, 8
|
||||
; SI-NEXT: s_lshl_b64 s[10:11], s[8:9], 8
|
||||
; SI-NEXT: s_and_b32 s15, s5, s25
|
||||
; SI-NEXT: s_lshl_b64 s[4:5], s[8:9], 24
|
||||
; SI-NEXT: s_lshl_b32 s29, s8, 24
|
||||
; SI-NEXT: s_lshl_b32 s4, s8, 8
|
||||
; SI-NEXT: v_and_b32_e32 v1, s31, v1
|
||||
; SI-NEXT: v_and_b32_e32 v0, s22, v0
|
||||
; SI-NEXT: s_and_b32 s12, s12, s27
|
||||
|
|
@ -377,28 +377,28 @@ define amdgpu_kernel void @test_bswap_v2i64(<2 x i64> addrspace(1)* %out, <2 x i
|
|||
; SI-NEXT: v_and_b32_e32 v3, s31, v3
|
||||
; SI-NEXT: v_and_b32_e32 v2, s22, v2
|
||||
; SI-NEXT: s_and_b32 s22, s32, s27
|
||||
; SI-NEXT: s_and_b32 s25, s7, s25
|
||||
; SI-NEXT: s_and_b32 s27, s9, s27
|
||||
; SI-NEXT: s_and_b32 s25, s11, s25
|
||||
; SI-NEXT: s_and_b32 s27, s5, s27
|
||||
; SI-NEXT: s_and_b32 s31, s4, s31
|
||||
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; SI-NEXT: s_or_b64 s[6:7], s[12:13], s[10:11]
|
||||
; SI-NEXT: s_or_b64 s[8:9], s[16:17], s[14:15]
|
||||
; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[6:7]
|
||||
; SI-NEXT: s_or_b64 s[10:11], s[16:17], s[14:15]
|
||||
; SI-NEXT: s_or_b64 s[12:13], s[18:19], s[20:21]
|
||||
; SI-NEXT: v_or_b32_e32 v1, v2, v3
|
||||
; SI-NEXT: s_lshr_b32 s10, s5, 24
|
||||
; SI-NEXT: s_or_b64 s[4:5], s[26:27], s[24:25]
|
||||
; SI-NEXT: s_lshr_b32 s6, s9, 24
|
||||
; SI-NEXT: s_or_b64 s[8:9], s[26:27], s[24:25]
|
||||
; SI-NEXT: s_or_b64 s[14:15], s[28:29], s[30:31]
|
||||
; SI-NEXT: v_or_b32_e32 v0, s6, v0
|
||||
; SI-NEXT: v_mov_b32_e32 v3, s7
|
||||
; SI-NEXT: s_or_b64 s[6:7], s[12:13], s[8:9]
|
||||
; SI-NEXT: s_or_b64 s[8:9], s[22:23], s[10:11]
|
||||
; SI-NEXT: s_or_b64 s[4:5], s[14:15], s[4:5]
|
||||
; SI-NEXT: v_or_b32_e32 v2, s6, v0
|
||||
; SI-NEXT: v_or_b32_e32 v3, s7, v3
|
||||
; SI-NEXT: v_or_b32_e32 v0, s8, v1
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s9
|
||||
; SI-NEXT: v_or_b32_e32 v0, s4, v0
|
||||
; SI-NEXT: v_or_b32_e32 v1, s5, v1
|
||||
; SI-NEXT: v_mov_b32_e32 v3, s5
|
||||
; SI-NEXT: s_or_b64 s[4:5], s[12:13], s[10:11]
|
||||
; SI-NEXT: s_or_b64 s[6:7], s[22:23], s[6:7]
|
||||
; SI-NEXT: s_or_b64 s[8:9], s[14:15], s[8:9]
|
||||
; SI-NEXT: v_or_b32_e32 v2, s4, v0
|
||||
; SI-NEXT: v_or_b32_e32 v3, s5, v3
|
||||
; SI-NEXT: v_or_b32_e32 v0, s6, v1
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s7
|
||||
; SI-NEXT: v_or_b32_e32 v0, s8, v0
|
||||
; SI-NEXT: v_or_b32_e32 v1, s9, v1
|
||||
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
|
|
|
|||
|
|
@ -314,26 +314,26 @@ define amdgpu_kernel void @test_copy_v4i8_extra_use(<4 x i8> addrspace(1)* %out0
|
|||
define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %out0, <4 x i8> addrspace(1)* %out1, <4 x i8> addrspace(1)* %out2, <4 x i8> addrspace(1)* %in) nounwind {
|
||||
; SI-LABEL: test_copy_v4i8_x2_extra_use:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
|
||||
; SI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s14, 0
|
||||
; SI-NEXT: s_mov_b32 s15, s11
|
||||
; SI-NEXT: s_mov_b32 s15, s3
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
|
||||
; SI-NEXT: s_mov_b64 s[12:13], s[10:11]
|
||||
; SI-NEXT: v_mov_b32_e32 v1, 0
|
||||
; SI-NEXT: buffer_load_dword v0, v[0:1], s[12:15], 0 addr64
|
||||
; SI-NEXT: s_mov_b32 s16, 0xff00
|
||||
; SI-NEXT: s_movk_i32 s17, 0xff
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_mov_b32 s8, s4
|
||||
; SI-NEXT: s_mov_b32 s9, s5
|
||||
; SI-NEXT: s_mov_b32 s4, s2
|
||||
; SI-NEXT: s_mov_b32 s5, s3
|
||||
; SI-NEXT: s_mov_b32 s6, s10
|
||||
; SI-NEXT: s_mov_b32 s7, s11
|
||||
; SI-NEXT: s_mov_b32 s2, s10
|
||||
; SI-NEXT: s_mov_b32 s3, s11
|
||||
; SI-NEXT: s_mov_b32 s2, -1
|
||||
; SI-NEXT: s_mov_b32 s0, s8
|
||||
; SI-NEXT: s_mov_b32 s1, s9
|
||||
; SI-NEXT: s_mov_b32 s8, s6
|
||||
; SI-NEXT: s_mov_b32 s9, s7
|
||||
; SI-NEXT: s_mov_b32 s10, s2
|
||||
; SI-NEXT: s_mov_b32 s11, s3
|
||||
; SI-NEXT: s_mov_b32 s6, s2
|
||||
; SI-NEXT: s_mov_b32 s7, s3
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_add_i32_e32 v3, vcc, 9, v0
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
||||
|
|
@ -349,9 +349,9 @@ define amdgpu_kernel void @test_copy_v4i8_x2_extra_use(<4 x i8> addrspace(1)* %o
|
|||
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
|
||||
; SI-NEXT: v_or_b32_e32 v1, v1, v2
|
||||
; SI-NEXT: v_add_i32_e32 v1, vcc, 0x9000000, v1
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_store_dword v1, off, s[8:11], 0
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-NEXT: buffer_store_dword v1, off, s[4:7], 0
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: test_copy_v4i8_x2_extra_use:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,28 @@
|
|||
; RUN: llc -march=amdgcn -verify-machineinstrs %s -o - | FileCheck %s
|
||||
|
||||
; CHECK-LABEL: foo
|
||||
; CHECK-NOT: BUFFER_LOAD_DWORDX2_OFFSET
|
||||
; After dead code elimination, that buffer load should be eliminated finally
|
||||
; after dead lane detection.
|
||||
define amdgpu_kernel void @foo() {
|
||||
entry:
|
||||
switch i8 undef, label %foo.exit [
|
||||
i8 4, label %sw.bb4
|
||||
i8 10, label %sw.bb10
|
||||
]
|
||||
|
||||
sw.bb4:
|
||||
%x = load i64, i64 addrspace(1)* undef, align 8
|
||||
%c = sitofp i64 %x to float
|
||||
%v = insertelement <2 x float> <float undef, float 0.000000e+00>, float %c, i32 0
|
||||
br label %foo.exit
|
||||
|
||||
sw.bb10:
|
||||
unreachable
|
||||
|
||||
foo.exit:
|
||||
%agg = phi <2 x float> [ %v, %sw.bb4 ], [ zeroinitializer, %entry ]
|
||||
%s = extractelement <2 x float> %agg, i32 1
|
||||
store float %s, float addrspace(1)* undef, align 4
|
||||
ret void
|
||||
}
|
||||
|
|
@ -1,55 +0,0 @@
|
|||
# RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -run-pass dead-mi-elimination -o - %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
# GCN-LABEL: name: dead_undef
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: S_ENDPGM 0
|
||||
---
|
||||
name: dead_undef
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
dead %2:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, undef %2:vgpr_32, implicit $exec
|
||||
S_ENDPGM 0
|
||||
|
||||
# GCN-LABEL: name: dead_defined
|
||||
# GCN: bb.0:
|
||||
# GCN-NEXT: S_ENDPGM 0
|
||||
---
|
||||
name: dead_defined
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = IMPLICIT_DEF
|
||||
dead %2:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, %2:vgpr_32, implicit $exec
|
||||
S_ENDPGM 0
|
||||
|
||||
# Probably this dead mac can be removed anyway.
|
||||
# GCN-LABEL: name: dead_def_live_use
|
||||
# GCN: dead %2:vgpr_32 = V_MAC_F32_e32 %0, %1, %2, implicit $exec
|
||||
---
|
||||
name: dead_def_live_use
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vgpr_32 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = IMPLICIT_DEF
|
||||
GLOBAL_STORE_DWORD undef $vgpr0_vgpr1, %2, 0, 0, 0, 0, implicit $exec
|
||||
dead %2:vgpr_32 = V_MAC_F32_e32 %0:vgpr_32, %1:vgpr_32, %2:vgpr_32, implicit $exec
|
||||
S_ENDPGM 0
|
||||
|
|
@ -254,17 +254,17 @@ entry:
|
|||
define amdgpu_kernel void @udot8_acc16(<8 x i4> addrspace(1)* %src1,
|
||||
; GFX7-LABEL: udot8_acc16:
|
||||
; GFX7: ; %bb.0: ; %entry
|
||||
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s11, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s10, -1
|
||||
; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s6, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_load_dword s0, s[4:5], 0x0
|
||||
; GFX7-NEXT: buffer_load_ushort v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[6:7], 0x0
|
||||
; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0
|
||||
; GFX7-NEXT: buffer_load_ushort v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[10:11], 0x0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s0, 28
|
||||
; GFX7-NEXT: s_bfe_u32 s4, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s8, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s15, s1, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s16, s1, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s17, s1, 0x40010
|
||||
|
|
@ -273,9 +273,9 @@ define amdgpu_kernel void @udot8_acc16(<8 x i4> addrspace(1)* %src1,
|
|||
; GFX7-NEXT: s_bfe_u32 s20, s1, 0x40004
|
||||
; GFX7-NEXT: s_lshr_b32 s14, s1, 28
|
||||
; GFX7-NEXT: s_and_b32 s1, s1, 15
|
||||
; GFX7-NEXT: s_bfe_u32 s5, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s6, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s7, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s9, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s10, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s11, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s12, s0, 0x40008
|
||||
; GFX7-NEXT: s_bfe_u32 s13, s0, 0x40004
|
||||
; GFX7-NEXT: s_and_b32 s0, s0, 15
|
||||
|
|
@ -290,13 +290,13 @@ define amdgpu_kernel void @udot8_acc16(<8 x i4> addrspace(1)* %src1,
|
|||
; GFX7-NEXT: v_mad_u32_u24 v0, s0, v1, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s13, v2, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s12, v3, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s7, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s6, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v7, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s10, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s9, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s8, v7, v0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s14
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s2, v1, v0
|
||||
; GFX7-NEXT: buffer_store_short v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: buffer_store_short v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX8-LABEL: udot8_acc16:
|
||||
|
|
@ -556,17 +556,17 @@ entry:
|
|||
define amdgpu_kernel void @udot8_acc8(<8 x i4> addrspace(1)* %src1,
|
||||
; GFX7-LABEL: udot8_acc8:
|
||||
; GFX7: ; %bb.0: ; %entry
|
||||
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s11, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s10, -1
|
||||
; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s6, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_load_dword s0, s[4:5], 0x0
|
||||
; GFX7-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[6:7], 0x0
|
||||
; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0
|
||||
; GFX7-NEXT: buffer_load_ubyte v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[10:11], 0x0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s0, 28
|
||||
; GFX7-NEXT: s_bfe_u32 s4, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s8, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s15, s1, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s16, s1, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s17, s1, 0x40010
|
||||
|
|
@ -575,9 +575,9 @@ define amdgpu_kernel void @udot8_acc8(<8 x i4> addrspace(1)* %src1,
|
|||
; GFX7-NEXT: s_bfe_u32 s20, s1, 0x40004
|
||||
; GFX7-NEXT: s_lshr_b32 s14, s1, 28
|
||||
; GFX7-NEXT: s_and_b32 s1, s1, 15
|
||||
; GFX7-NEXT: s_bfe_u32 s5, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s6, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s7, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s9, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s10, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s11, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s12, s0, 0x40008
|
||||
; GFX7-NEXT: s_bfe_u32 s13, s0, 0x40004
|
||||
; GFX7-NEXT: s_and_b32 s0, s0, 15
|
||||
|
|
@ -592,13 +592,13 @@ define amdgpu_kernel void @udot8_acc8(<8 x i4> addrspace(1)* %src1,
|
|||
; GFX7-NEXT: v_mad_u32_u24 v0, s0, v1, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s13, v2, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s12, v3, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s7, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s6, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v7, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s10, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s9, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s8, v7, v0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s14
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s2, v1, v0
|
||||
; GFX7-NEXT: buffer_store_byte v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: buffer_store_byte v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX8-LABEL: udot8_acc8:
|
||||
|
|
@ -858,17 +858,17 @@ entry:
|
|||
define amdgpu_kernel void @udot8_acc4(<8 x i4> addrspace(1)* %src1,
|
||||
; GFX7-LABEL: udot8_acc4:
|
||||
; GFX7: ; %bb.0: ; %entry
|
||||
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s11, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s10, -1
|
||||
; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s6, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_load_dword s0, s[4:5], 0x0
|
||||
; GFX7-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[6:7], 0x0
|
||||
; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0
|
||||
; GFX7-NEXT: buffer_load_ubyte v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[10:11], 0x0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s0, 28
|
||||
; GFX7-NEXT: s_bfe_u32 s4, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s8, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s15, s1, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s16, s1, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s17, s1, 0x40010
|
||||
|
|
@ -877,9 +877,9 @@ define amdgpu_kernel void @udot8_acc4(<8 x i4> addrspace(1)* %src1,
|
|||
; GFX7-NEXT: s_bfe_u32 s20, s1, 0x40004
|
||||
; GFX7-NEXT: s_lshr_b32 s14, s1, 28
|
||||
; GFX7-NEXT: s_and_b32 s1, s1, 15
|
||||
; GFX7-NEXT: s_bfe_u32 s5, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s6, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s7, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s9, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s10, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s11, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s12, s0, 0x40008
|
||||
; GFX7-NEXT: s_bfe_u32 s13, s0, 0x40004
|
||||
; GFX7-NEXT: s_and_b32 s0, s0, 15
|
||||
|
|
@ -894,14 +894,14 @@ define amdgpu_kernel void @udot8_acc4(<8 x i4> addrspace(1)* %src1,
|
|||
; GFX7-NEXT: v_mad_u32_u24 v0, s0, v1, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s13, v2, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s12, v3, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s7, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s6, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v7, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s10, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s9, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s8, v7, v0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s14
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s2, v1, v0
|
||||
; GFX7-NEXT: v_and_b32_e32 v0, 15, v0
|
||||
; GFX7-NEXT: buffer_store_byte v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: buffer_store_byte v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX8-LABEL: udot8_acc4:
|
||||
|
|
@ -1157,17 +1157,17 @@ entry:
|
|||
define amdgpu_kernel void @udot8_CommutationInsideMAD(<8 x i4> addrspace(1)* %src1,
|
||||
; GFX7-LABEL: udot8_CommutationInsideMAD:
|
||||
; GFX7: ; %bb.0: ; %entry
|
||||
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s11, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s10, -1
|
||||
; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s6, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_load_dword s0, s[4:5], 0x0
|
||||
; GFX7-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[6:7], 0x0
|
||||
; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0
|
||||
; GFX7-NEXT: buffer_load_ubyte v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[10:11], 0x0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s0, 28
|
||||
; GFX7-NEXT: s_bfe_u32 s4, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s8, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s15, s1, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s16, s1, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s17, s1, 0x40010
|
||||
|
|
@ -1176,9 +1176,9 @@ define amdgpu_kernel void @udot8_CommutationInsideMAD(<8 x i4> addrspace(1)* %sr
|
|||
; GFX7-NEXT: s_bfe_u32 s20, s1, 0x40004
|
||||
; GFX7-NEXT: s_lshr_b32 s14, s1, 28
|
||||
; GFX7-NEXT: s_and_b32 s1, s1, 15
|
||||
; GFX7-NEXT: s_bfe_u32 s5, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s6, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s7, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s9, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s10, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s11, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s12, s0, 0x40008
|
||||
; GFX7-NEXT: s_bfe_u32 s13, s0, 0x40004
|
||||
; GFX7-NEXT: s_and_b32 s0, s0, 15
|
||||
|
|
@ -1193,14 +1193,14 @@ define amdgpu_kernel void @udot8_CommutationInsideMAD(<8 x i4> addrspace(1)* %sr
|
|||
; GFX7-NEXT: v_mad_u32_u24 v0, s0, v1, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s13, v2, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s12, v3, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s7, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s6, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v7, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s10, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s9, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s8, v7, v0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s14
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s2, v1, v0
|
||||
; GFX7-NEXT: v_and_b32_e32 v0, 15, v0
|
||||
; GFX7-NEXT: buffer_store_byte v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: buffer_store_byte v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX8-LABEL: udot8_CommutationInsideMAD:
|
||||
|
|
@ -2645,17 +2645,17 @@ entry:
|
|||
define amdgpu_kernel void @udot8_acc4_vecMul(<8 x i4> addrspace(1)* %src1,
|
||||
; GFX7-LABEL: udot8_acc4_vecMul:
|
||||
; GFX7: ; %bb.0: ; %entry
|
||||
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s11, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s10, -1
|
||||
; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
|
||||
; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
|
||||
; GFX7-NEXT: s_mov_b32 s7, 0xf000
|
||||
; GFX7-NEXT: s_mov_b32 s6, -1
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_load_dword s0, s[4:5], 0x0
|
||||
; GFX7-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[6:7], 0x0
|
||||
; GFX7-NEXT: s_load_dword s0, s[8:9], 0x0
|
||||
; GFX7-NEXT: buffer_load_ubyte v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_load_dword s1, s[10:11], 0x0
|
||||
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GFX7-NEXT: s_lshr_b32 s2, s0, 28
|
||||
; GFX7-NEXT: s_bfe_u32 s4, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s8, s0, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s15, s1, 0x40018
|
||||
; GFX7-NEXT: s_bfe_u32 s16, s1, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s17, s1, 0x40010
|
||||
|
|
@ -2664,9 +2664,9 @@ define amdgpu_kernel void @udot8_acc4_vecMul(<8 x i4> addrspace(1)* %src1,
|
|||
; GFX7-NEXT: s_bfe_u32 s20, s1, 0x40004
|
||||
; GFX7-NEXT: s_lshr_b32 s14, s1, 28
|
||||
; GFX7-NEXT: s_and_b32 s1, s1, 15
|
||||
; GFX7-NEXT: s_bfe_u32 s5, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s6, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s7, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s9, s0, 0x40014
|
||||
; GFX7-NEXT: s_bfe_u32 s10, s0, 0x40010
|
||||
; GFX7-NEXT: s_bfe_u32 s11, s0, 0x4000c
|
||||
; GFX7-NEXT: s_bfe_u32 s12, s0, 0x40008
|
||||
; GFX7-NEXT: s_bfe_u32 s13, s0, 0x40004
|
||||
; GFX7-NEXT: s_and_b32 s0, s0, 15
|
||||
|
|
@ -2681,14 +2681,14 @@ define amdgpu_kernel void @udot8_acc4_vecMul(<8 x i4> addrspace(1)* %src1,
|
|||
; GFX7-NEXT: v_mad_u32_u24 v0, s0, v1, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s13, v2, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s12, v3, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s7, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s6, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s5, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s4, v7, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s11, v4, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s10, v5, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s9, v6, v0
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s8, v7, v0
|
||||
; GFX7-NEXT: v_mov_b32_e32 v1, s14
|
||||
; GFX7-NEXT: v_mad_u32_u24 v0, s2, v1, v0
|
||||
; GFX7-NEXT: v_and_b32_e32 v0, 15, v0
|
||||
; GFX7-NEXT: buffer_store_byte v0, off, s[8:11], 0
|
||||
; GFX7-NEXT: buffer_store_byte v0, off, s[4:7], 0
|
||||
; GFX7-NEXT: s_endpgm
|
||||
;
|
||||
; GFX8-LABEL: udot8_acc4_vecMul:
|
||||
|
|
|
|||
|
|
@ -1617,31 +1617,31 @@ define amdgpu_kernel void @dynamic_insertelement_v4f64(<4 x double> addrspace(1)
|
|||
define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %a, i32 %b) #0 {
|
||||
; SI-LABEL: dynamic_insertelement_v8f64:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_load_dwordx2 s[24:25], s[4:5], 0x0
|
||||
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x10
|
||||
; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
|
||||
; SI-NEXT: s_load_dwordx16 s[12:27], s[4:5], 0x10
|
||||
; SI-NEXT: s_load_dword s4, s[4:5], 0x20
|
||||
; SI-NEXT: v_mov_b32_e32 v16, 64
|
||||
; SI-NEXT: s_mov_b32 s27, 0x100f000
|
||||
; SI-NEXT: s_mov_b32 s26, -1
|
||||
; SI-NEXT: s_mov_b32 s11, 0x100f000
|
||||
; SI-NEXT: s_mov_b32 s10, -1
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s8
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s12
|
||||
; SI-NEXT: s_and_b32 s4, s4, 7
|
||||
; SI-NEXT: s_lshl_b32 s4, s4, 3
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s9
|
||||
; SI-NEXT: v_mov_b32_e32 v2, s10
|
||||
; SI-NEXT: v_mov_b32_e32 v3, s11
|
||||
; SI-NEXT: v_mov_b32_e32 v4, s12
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s13
|
||||
; SI-NEXT: v_mov_b32_e32 v6, s14
|
||||
; SI-NEXT: v_mov_b32_e32 v7, s15
|
||||
; SI-NEXT: v_mov_b32_e32 v8, s16
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s17
|
||||
; SI-NEXT: v_mov_b32_e32 v10, s18
|
||||
; SI-NEXT: v_mov_b32_e32 v11, s19
|
||||
; SI-NEXT: v_mov_b32_e32 v12, s20
|
||||
; SI-NEXT: v_mov_b32_e32 v13, s21
|
||||
; SI-NEXT: v_mov_b32_e32 v14, s22
|
||||
; SI-NEXT: v_mov_b32_e32 v15, s23
|
||||
; SI-NEXT: v_mov_b32_e32 v1, s13
|
||||
; SI-NEXT: v_mov_b32_e32 v2, s14
|
||||
; SI-NEXT: v_mov_b32_e32 v3, s15
|
||||
; SI-NEXT: v_mov_b32_e32 v4, s16
|
||||
; SI-NEXT: v_mov_b32_e32 v5, s17
|
||||
; SI-NEXT: v_mov_b32_e32 v6, s18
|
||||
; SI-NEXT: v_mov_b32_e32 v7, s19
|
||||
; SI-NEXT: v_mov_b32_e32 v8, s20
|
||||
; SI-NEXT: v_mov_b32_e32 v9, s21
|
||||
; SI-NEXT: v_mov_b32_e32 v10, s22
|
||||
; SI-NEXT: v_mov_b32_e32 v11, s23
|
||||
; SI-NEXT: v_mov_b32_e32 v12, s24
|
||||
; SI-NEXT: v_mov_b32_e32 v13, s25
|
||||
; SI-NEXT: v_mov_b32_e32 v14, s26
|
||||
; SI-NEXT: v_mov_b32_e32 v15, s27
|
||||
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], s7 offset:112
|
||||
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], s7 offset:80
|
||||
|
|
@ -1655,39 +1655,40 @@ define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)
|
|||
; SI-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; SI-NEXT: buffer_load_dwordx4 v[12:15], off, s[0:3], s7 offset:112
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[24:27], 0 offset:48
|
||||
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[24:27], 0 offset:32
|
||||
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:16
|
||||
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[24:27], 0
|
||||
; SI-NEXT: buffer_store_dwordx4 v[12:15], off, s[8:11], 0 offset:48
|
||||
; SI-NEXT: buffer_store_dwordx4 v[8:11], off, s[8:11], 0 offset:32
|
||||
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
|
||||
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: dynamic_insertelement_v8f64:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_load_dwordx2 s[24:25], s[4:5], 0x0
|
||||
; VI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x40
|
||||
; VI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0
|
||||
; VI-NEXT: s_load_dwordx16 s[12:27], s[4:5], 0x40
|
||||
; VI-NEXT: s_load_dword s4, s[4:5], 0x80
|
||||
; VI-NEXT: v_mov_b32_e32 v16, 64
|
||||
; VI-NEXT: s_mov_b32 s27, 0x1100f000
|
||||
; VI-NEXT: s_mov_b32 s26, -1
|
||||
; VI-NEXT: s_mov_b32 s11, 0x1100f000
|
||||
; VI-NEXT: s_mov_b32 s10, -1
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: v_mov_b32_e32 v0, s8
|
||||
; VI-NEXT: v_mov_b32_e32 v0, s12
|
||||
; VI-NEXT: s_and_b32 s4, s4, 7
|
||||
; VI-NEXT: s_lshl_b32 s4, s4, 3
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s9
|
||||
; VI-NEXT: v_mov_b32_e32 v2, s10
|
||||
; VI-NEXT: v_mov_b32_e32 v3, s11
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s12
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s13
|
||||
; VI-NEXT: v_mov_b32_e32 v6, s14
|
||||
; VI-NEXT: v_mov_b32_e32 v7, s15
|
||||
; VI-NEXT: v_mov_b32_e32 v8, s16
|
||||
; VI-NEXT: v_mov_b32_e32 v9, s17
|
||||
; VI-NEXT: v_mov_b32_e32 v10, s18
|
||||
; VI-NEXT: v_mov_b32_e32 v11, s19
|
||||
; VI-NEXT: v_mov_b32_e32 v12, s20
|
||||
; VI-NEXT: v_mov_b32_e32 v13, s21
|
||||
; VI-NEXT: v_mov_b32_e32 v14, s22
|
||||
; VI-NEXT: v_mov_b32_e32 v15, s23
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s13
|
||||
; VI-NEXT: v_mov_b32_e32 v2, s14
|
||||
; VI-NEXT: v_mov_b32_e32 v3, s15
|
||||
; VI-NEXT: v_mov_b32_e32 v4, s16
|
||||
; VI-NEXT: v_mov_b32_e32 v5, s17
|
||||
; VI-NEXT: v_mov_b32_e32 v6, s18
|
||||
; VI-NEXT: v_mov_b32_e32 v7, s19
|
||||
; VI-NEXT: v_mov_b32_e32 v8, s20
|
||||
; VI-NEXT: v_mov_b32_e32 v9, s21
|
||||
; VI-NEXT: v_mov_b32_e32 v10, s22
|
||||
; VI-NEXT: v_mov_b32_e32 v11, s23
|
||||
; VI-NEXT: v_mov_b32_e32 v12, s24
|
||||
; VI-NEXT: v_mov_b32_e32 v13, s25
|
||||
; VI-NEXT: v_mov_b32_e32 v14, s26
|
||||
; VI-NEXT: v_mov_b32_e32 v15, s27
|
||||
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], s7 offset:112
|
||||
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], s7 offset:80
|
||||
|
|
@ -1701,10 +1702,10 @@ define amdgpu_kernel void @dynamic_insertelement_v8f64(<8 x double> addrspace(1)
|
|||
; VI-NEXT: buffer_load_dwordx4 v[8:11], off, s[0:3], s7 offset:96
|
||||
; VI-NEXT: buffer_load_dwordx4 v[12:15], off, s[0:3], s7 offset:112
|
||||
; VI-NEXT: s_waitcnt vmcnt(0)
|
||||
; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[24:27], 0 offset:48
|
||||
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[24:27], 0 offset:32
|
||||
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[24:27], 0 offset:16
|
||||
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[24:27], 0
|
||||
; VI-NEXT: buffer_store_dwordx4 v[12:15], off, s[8:11], 0 offset:48
|
||||
; VI-NEXT: buffer_store_dwordx4 v[8:11], off, s[8:11], 0 offset:32
|
||||
; VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
|
||||
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
|
||||
; VI-NEXT: s_endpgm
|
||||
%vecins = insertelement <8 x double> %a, double 8.0, i32 %b
|
||||
store <8 x double> %vecins, <8 x double> addrspace(1)* %out, align 16
|
||||
|
|
|
|||
|
|
@ -15,13 +15,13 @@ define amdgpu_cs float @ds_ordered_swap(i32 addrspace(2)* inreg %gds, i32 %value
|
|||
}
|
||||
|
||||
; FUNC-LABEL: {{^}}ds_ordered_swap_conditional:
|
||||
; GCN: v_cmp_ne_u32_e32 vcc, 0, v0
|
||||
; GCN: v_cmp_ne_u32_e32 vcc, 0, v[[VALUE:[0-9]+]]
|
||||
; GCN: s_and_saveexec_b64 s[[SAVED:\[[0-9]+:[0-9]+\]]], vcc
|
||||
; // We have to use s_cbranch, because ds_ordered_count has side effects with EXEC=0
|
||||
; GCN: s_cbranch_execz [[BB:BB._.]]
|
||||
; GCN: s_mov_b32 m0, s0
|
||||
; VIGFX9-NEXT: s_nop 0
|
||||
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v0 offset:4868 gds
|
||||
; GCN-NEXT: ds_ordered_count v{{[0-9]+}}, v[[VALUE]] offset:4868 gds
|
||||
; GCN-NEXT: [[BB]]:
|
||||
; // Wait for expcnt(0) before modifying EXEC
|
||||
; GCN-NEXT: s_waitcnt expcnt(0)
|
||||
|
|
|
|||
|
|
@ -393,47 +393,47 @@ define amdgpu_kernel void @round_v4f64(<4 x double> addrspace(1)* %out, <4 x dou
|
|||
;
|
||||
; CI-LABEL: round_v4f64:
|
||||
; CI: ; %bb.0:
|
||||
; CI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x9
|
||||
; CI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x11
|
||||
; CI-NEXT: s_brev_b32 s12, -2
|
||||
; CI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
|
||||
; CI-NEXT: s_load_dwordx8 s[8:15], s[0:1], 0x11
|
||||
; CI-NEXT: s_brev_b32 s2, -2
|
||||
; CI-NEXT: v_mov_b32_e32 v12, 0x3ff00000
|
||||
; CI-NEXT: s_mov_b32 s11, 0xf000
|
||||
; CI-NEXT: s_mov_b32 s10, -1
|
||||
; CI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; CI-NEXT: s_mov_b32 s6, -1
|
||||
; CI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[2:3]
|
||||
; CI-NEXT: v_mov_b32_e32 v4, s3
|
||||
; CI-NEXT: v_add_f64 v[2:3], s[2:3], -v[0:1]
|
||||
; CI-NEXT: v_bfi_b32 v4, s12, v12, v4
|
||||
; CI-NEXT: v_trunc_f64_e32 v[0:1], s[10:11]
|
||||
; CI-NEXT: v_mov_b32_e32 v4, s11
|
||||
; CI-NEXT: v_add_f64 v[2:3], s[10:11], -v[0:1]
|
||||
; CI-NEXT: v_bfi_b32 v4, s2, v12, v4
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[2:3]|, 0.5
|
||||
; CI-NEXT: v_trunc_f64_e32 v[8:9], s[0:1]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[8:9], s[8:9]
|
||||
; CI-NEXT: v_cndmask_b32_e32 v3, 0, v4, vcc
|
||||
; CI-NEXT: v_mov_b32_e32 v2, 0
|
||||
; CI-NEXT: v_add_f64 v[2:3], v[0:1], v[2:3]
|
||||
; CI-NEXT: v_add_f64 v[0:1], s[0:1], -v[8:9]
|
||||
; CI-NEXT: v_mov_b32_e32 v4, s1
|
||||
; CI-NEXT: v_add_f64 v[0:1], s[8:9], -v[8:9]
|
||||
; CI-NEXT: v_mov_b32_e32 v4, s9
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[0:1]|, 0.5
|
||||
; CI-NEXT: v_bfi_b32 v4, s12, v12, v4
|
||||
; CI-NEXT: v_bfi_b32 v4, s2, v12, v4
|
||||
; CI-NEXT: v_cndmask_b32_e32 v1, 0, v4, vcc
|
||||
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[6:7]
|
||||
; CI-NEXT: v_mov_b32_e32 v10, s7
|
||||
; CI-NEXT: v_add_f64 v[6:7], s[6:7], -v[4:5]
|
||||
; CI-NEXT: v_bfi_b32 v10, s12, v12, v10
|
||||
; CI-NEXT: v_trunc_f64_e32 v[4:5], s[14:15]
|
||||
; CI-NEXT: v_mov_b32_e32 v10, s15
|
||||
; CI-NEXT: v_add_f64 v[6:7], s[14:15], -v[4:5]
|
||||
; CI-NEXT: v_bfi_b32 v10, s2, v12, v10
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[6:7]|, 0.5
|
||||
; CI-NEXT: v_mov_b32_e32 v6, 0
|
||||
; CI-NEXT: v_cndmask_b32_e32 v7, 0, v10, vcc
|
||||
; CI-NEXT: v_trunc_f64_e32 v[10:11], s[4:5]
|
||||
; CI-NEXT: v_trunc_f64_e32 v[10:11], s[12:13]
|
||||
; CI-NEXT: v_add_f64 v[6:7], v[4:5], v[6:7]
|
||||
; CI-NEXT: v_add_f64 v[4:5], s[4:5], -v[10:11]
|
||||
; CI-NEXT: v_mov_b32_e32 v13, s5
|
||||
; CI-NEXT: v_add_f64 v[4:5], s[12:13], -v[10:11]
|
||||
; CI-NEXT: v_mov_b32_e32 v13, s13
|
||||
; CI-NEXT: v_cmp_ge_f64_e64 vcc, |v[4:5]|, 0.5
|
||||
; CI-NEXT: v_bfi_b32 v12, s12, v12, v13
|
||||
; CI-NEXT: v_bfi_b32 v12, s2, v12, v13
|
||||
; CI-NEXT: v_mov_b32_e32 v0, 0
|
||||
; CI-NEXT: v_cndmask_b32_e32 v5, 0, v12, vcc
|
||||
; CI-NEXT: v_mov_b32_e32 v4, 0
|
||||
; CI-NEXT: v_add_f64 v[4:5], v[10:11], v[4:5]
|
||||
; CI-NEXT: v_add_f64 v[0:1], v[8:9], v[0:1]
|
||||
; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:16
|
||||
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
|
||||
; CI-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
|
||||
; CI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
||||
; CI-NEXT: s_endpgm
|
||||
%result = call <4 x double> @llvm.round.v4f64(<4 x double> %in) #1
|
||||
store <4 x double> %result, <4 x double> addrspace(1)* %out
|
||||
|
|
|
|||
|
|
@ -26,9 +26,9 @@
|
|||
; GCN: s_mov_b64 [[ACCUM_MASK:s\[[0-9]+:[0-9]+\]]], 0{{$}}
|
||||
|
||||
; GCN: [[LOOP_ENTRY:BB[0-9]+_[0-9]+]]: ; %bb1
|
||||
; GCN: s_add_i32 s4, s4, 1
|
||||
; GCN: s_add_i32 s6, s6, 1
|
||||
; GCN: s_or_b64 [[INNER_MASK:s\[[0-9]+:[0-9]+\]]], [[INNER_MASK]], exec
|
||||
; GCN: s_cmp_gt_i32 s4, -1
|
||||
; GCN: s_cmp_gt_i32 s6, -1
|
||||
; GCN: s_cbranch_scc1 [[FLOW:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN: ; %bb4
|
||||
|
|
|
|||
|
|
@ -395,28 +395,28 @@ define amdgpu_kernel void @select_v2f16(
|
|||
; SI-LABEL: select_v2f16:
|
||||
; SI: ; %bb.0: ; %entry
|
||||
; SI-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x9
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x11
|
||||
; SI-NEXT: s_mov_b32 s15, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s14, -1
|
||||
; SI-NEXT: s_mov_b32 s22, s14
|
||||
; SI-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x11
|
||||
; SI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s2, -1
|
||||
; SI-NEXT: s_mov_b32 s22, s2
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s16, s10
|
||||
; SI-NEXT: s_mov_b32 s17, s11
|
||||
; SI-NEXT: s_mov_b32 s10, s14
|
||||
; SI-NEXT: s_mov_b32 s11, s15
|
||||
; SI-NEXT: s_mov_b32 s10, s2
|
||||
; SI-NEXT: s_mov_b32 s11, s3
|
||||
; SI-NEXT: s_mov_b32 s20, s6
|
||||
; SI-NEXT: s_mov_b32 s21, s7
|
||||
; SI-NEXT: s_mov_b32 s23, s15
|
||||
; SI-NEXT: s_mov_b32 s2, s14
|
||||
; SI-NEXT: s_mov_b32 s3, s15
|
||||
; SI-NEXT: s_mov_b32 s23, s3
|
||||
; SI-NEXT: s_mov_b32 s14, s2
|
||||
; SI-NEXT: s_mov_b32 s15, s3
|
||||
; SI-NEXT: buffer_load_dword v0, off, s[20:23], 0
|
||||
; SI-NEXT: s_mov_b32 s18, s14
|
||||
; SI-NEXT: s_mov_b32 s19, s15
|
||||
; SI-NEXT: s_mov_b32 s18, s2
|
||||
; SI-NEXT: s_mov_b32 s19, s3
|
||||
; SI-NEXT: buffer_load_dword v1, off, s[8:11], 0
|
||||
; SI-NEXT: buffer_load_dword v2, off, s[0:3], 0
|
||||
; SI-NEXT: buffer_load_dword v2, off, s[12:15], 0
|
||||
; SI-NEXT: buffer_load_dword v3, off, s[16:19], 0
|
||||
; SI-NEXT: s_mov_b32 s12, s4
|
||||
; SI-NEXT: s_mov_b32 s13, s5
|
||||
; SI-NEXT: s_mov_b32 s0, s4
|
||||
; SI-NEXT: s_mov_b32 s1, s5
|
||||
; SI-NEXT: s_waitcnt vmcnt(3)
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v0
|
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; SI-NEXT: v_cvt_f32_f16_e32 v5, v5
|
||||
|
|
@ -441,7 +441,7 @@ define amdgpu_kernel void @select_v2f16(
|
|||
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
||||
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[12:15], 0
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: select_v2f16:
|
||||
|
|
|
|||
|
|
@ -246,7 +246,7 @@ define amdgpu_kernel void @max_256_vgprs_spill_9x32(<32 x float> addrspace(1)* %
|
|||
; GFX908-DAG v_accvgpr_read_b32
|
||||
|
||||
; GCN: NumVgprs: 256
|
||||
; GFX900: ScratchSize: 580
|
||||
; GFX900: ScratchSize: 644
|
||||
; GFX908-FIXME: ScratchSize: 0
|
||||
; GCN: VGPRBlocks: 63
|
||||
; GCN: NumVGPRsForWavesPerEU: 256
|
||||
|
|
|
|||
Loading…
Reference in New Issue